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Description: OK6410的led裸机程序
注：烧写bootloader 的目的是让开发板上电时对PLL,DDR RAM 进行初始化。以便把程序加
载到内存中进行调-Note: The purpose is to allow programming the bootloader development board is powered on PLL, DDR RAM is initialized. So that the program is loaded into memory for tone
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Size: 144384 |
Author: zxl |
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Description: direct帮助文档很详细有demo,开发必备-direct help documentation is very detailed, demo, development of essential
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Size: 276480 |
Author: tolinda |
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Description: 详细的讲解了当前流行的几种主要的NAND FLASH接口特性，包括SDR、DDR NAND FLASH-Detailed explanation of the current popular several major NAND FLASH interface characteristics, including SDR, DDR NAND FLASH
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Size: 4305920 |
Author: bot |
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Description: 某培训机构，基于s3c6410的裸机代码：包括最初的函数(汇编编写)和Makefile 以及时钟、串口、DDR、nand flash、LCD、链接脚本的裸机代码。-A training organization, based s3c6410 bare metal code: including the initial function (compilation prepared) and Makefile and the clock, serial, DDR, nand flash, LCD bare metal code.
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Size: 7168 |
Author: 李泽源 |
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Description: 210的ddr裸机，绝对原创,是裸板哦，不是驱动-210 ddr
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Size: 13312 |
Author: wanyong |
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Description: K4X2G323完整数据手册，三星DDR SDRAM芯片，128MB-K4X2G323 datasheet
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Size: 354304 |
Author: 王文静 |
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Description: davinci平台dm8168外接DDR3功能测试-davinci dm8168 external DDR3 functional test platform
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Size: 51200 |
Author: zhangchuntao |
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Description: 基于ARM 的S3C6410 DDR内存的驱动，实现了内存的初始化等-The driver of DDR
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Size: 15360 |
Author: 岳云 |
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Description: 用于FPGA内部计数辅助DDR操作，便于开发-TimeOut Counter
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Size: 1024 |
Author: wang |
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Description: DDR3控制器，用于FPGA内部对DDR进行操作，利用Avlone总线进行对接-DDR controller
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Size: 7168 |
Author: wang |
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Description: DSP_EVMDM6437开发版的ddr测试源码，检测开发板两片内存的硬件好坏。-the EVMDM6437_ddr_test can test the one of both the chip of ddr on the board.
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Size: 1024 |
Author: 安捷伦 |
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Description: modelsim，micron公司的ddr sdram仿真模型，verilog。-modelsim，micron，ddr sdram simulat module，verilog。
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Size: 40960 |
Author: 黄志沛 |
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Description: FPGA外部的ddr2设计的相关学习资料-off-fpga，ddr design
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Size: 182272 |
Author: 黄志沛 |
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Description: A 0.31–1 GHz Fast-Corrected Duty-Cycle Corrector
With Successive Approximation Register for DDR DRAM Applications
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Size: 416768 |
Author: rajapraba |
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Description: DDR addressing details and AC timing parameters from JEDEC specs.
Platform: |
Size: 1024 |
Author: qeilagui |
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Description: ddr mmu nand的裸板驱动 在exynos4412板子上运行 关掉mmu可试验 arm汇编代码-DDR mmu nand bare plate drive run on exynos4412 boards off mmu can test arm assembly code
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Size: 2769920 |
Author: 黄流飞 |
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Description: DSP_EVMDM6437开发版的ddr测试源码，检测开发板两片内存的硬件好坏。-the EVMDM6437_ddr_test can test the one of both the chip of ddr on the board.
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Size: 1024 |
Author: ndqua |
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Description: DDRSDRAM Verilog以及中文解释-DDRSDRAM Verilog
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Size: 481280 |
Author: 丁昊天 |
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Description: xilinx赛灵思的DDR控制器源码（包括仿真与说明文档），DDR为mt46v4m16。-Xilinx DDR controller source code (including simulation and documentation), DDR is mt46v4m16.
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Size: 131072 |
Author: 刘佳庆 |
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Description: altera的DDR控制器源码（包括仿真与说明文档），DDR为mt46v4m16，Verilog-The DDR controller source of altera (including simulation and documentation), DDR is mt46v4m16, Verilog
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Size: 753664 |
Author: 刘佳庆 |
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