Search - USB2.0 IP

[USB develop] USB2.0_rtl_ipcore_verilog

Description: 经过门级网单验证的USB2.0 IP核 RTL代码-net after gate-level verification of USB IP Core RTL code
Platform: | Size: 62383 | Author: 王椿棠 | Hits:

[Other resource] USB2.0IP_core_Verilog

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
Platform: | Size: 206883 | Author: 张清平 | Hits:

[USB develop] usb_funct

Description: usb2.0 ip 文挡齐全,并已经过FPGA的验证,希望大家支持
Platform: | Size: 209311 | Author: kin | Hits:

[VHDL-FPGA-Verilog] USB2.0 IP核

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件
Platform: | Size: 232984 | Author: L2U2M6 | Hits:

[USB develop] USB2_chip

Description: USB2.0 chip的一部分verilog源码。opencore上下的，还比较好用:)-USB2.0 chip part of Verilog source. Opencore ish, but also better quality :)
Platform: | Size: 35840 | Author: 戴鹏 | Hits:

[VHDL-FPGA-Verilog] USB2.0IP_core_Verilog

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
Platform: | Size: 206848 | Author: 张清平 | Hits:

[VHDL-FPGA-Verilog] usb_funct[1].tar

Description: usb2.0的IP核，可在QuartusII或MaxPlusII环境下实现编译和生成ip核-usb2.0 IP nuclear, QuartusII or the environment under MaxPlusII compile and generate nuclear ip
Platform: | Size: 181248 | Author: 刘洋 | Hits:

[USB develop] usb_funct

Description: usb2.0 ip 文挡齐全,并已经过FPGA的验证,希望大家支持-usb2.0 ip complete text block, and has been FPGA verification, I hope you will support
Platform: | Size: 208896 | Author: kin | Hits:

[Software Engineering] WNUSB

Description: [UsbKbd.rar] - usbkbd,用wdm编写的usb和键盘的驱动示例 [USB2.0_USB_driver.rar] - 学习USB2.0驱动程序设计源码，包括Windows DDK Driver驱动的详细设计，U盘，MP3的程序设计例子 [mc8051_design.zip] - MC8051 IP CoreOregano Systems 8-bit Microcontroller IP-Core此公司提供的8051 -[UsbKbd.rar]- usbkbd, prepared with wdm drivers usb and keyboard sample [USB2.0_USB_driver.rar]- Learning USB2.0 Driver source, including the Windows DDK Driver drive the detailed design, U disk, MP3
Platform: | Size: 23552 | Author: 王军 | Hits:

[VHDL-FPGA-Verilog] USB2.0IP

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码,包括文档-Complete Verilog language developed by USB2.0 IP core source code, including documentation
Platform: | Size: 206848 | Author: 陈润 | Hits:

[Software Engineering] USB_IP

Description: 介绍了采用FPGA实现USB2.0 IP核的详细方法和步骤以及仿真方法-This paper introduces an FPGA to achieve the USB2.0 IP core in detail the methods and steps as well as the simulation method
Platform: | Size: 1610752 | Author: Tomy Lee | Hits:

[VHDL-FPGA-Verilog] VERILOG-USB2.0IP-core

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-VERILOG language with a complete development of USB2.0 IP core source code, including files, simulation files
Platform: | Size: 220160 | Author: king | Hits:

[Software Engineering] USB2.0DeviceControllerIPCoreDesignandVerification.

Description: USB2．0设备控制器IP核的设计与验证-USB2.0 Device Controller IP Core Design and Verification
Platform: | Size: 432128 | Author: 许云涛 | Hits:

[VHDL-FPGA-Verilog] USB2.0IP(RTL)

Description: USB2.0 IP核,ASIC,FPGA可用,Verilog HDL源代码-USB2.0 IP,Verilog HDL
Platform: | Size: 64512 | Author: AmazingEric | Hits:

[VHDL-FPGA-Verilog] USB2.0-IP-core

Description: 用verilog 写的USB2.0，含源码。从别处找来的，不敢独享，希望对大家有帮助-Written by verilog USB2.0, including source code. Recruited from elsewhere, and not exclusive, we want to help
Platform: | Size: 200704 | Author: 柳同学 | Hits:

[VHDL-FPGA-Verilog] verilog-usb--protel-design

Description: 基于FPGA的usb2.0 ip核设计，所用的语言是verilog-FPGA-based usb2.0 ip core design, the language used is the verilog
Platform: | Size: 53248 | Author: 唐明桂 | Hits:

[VHDL-FPGA-Verilog] USB2.0-IP

Description: USB2.0 IP核源代码，经典好用！写这么多真没意思！-USB 2.0 IP core source code, easy to use classic! Write so really boring!
Platform: | Size: 229376 | Author: sulianghe | Hits:

[VHDL-FPGA-Verilog] USB2.0IP

Description: usb2.0的IP核，对于USB接口通信的FPGA设计有很大帮助，对于接口硬件的控制更为灵活。有详尽的USB2.0协议说明-usb2.0 IP core for FPGA design of the USB interface communication, more flexible control interface hardware. Detailed USB2.0 protocol description
Platform: | Size: 206848 | Author: 张奎 | Hits:

[VHDL-FPGA-Verilog] USB2.0IPcoredesign

Description: USB2.0的IP核开发.代码可以直接使用已经验证过。-USB2.0 IP core development. Code can be directly used has already been verified.
Platform: | Size: 6250496 | Author: 赵小强 | Hits:

[VHDL-FPGA-Verilog] USB2.0的IP核（详细verilog源码和文档）

Description: USB2.0的IP核开发.代码可以直接使用已经验证过(USB2.0 IP kernel development. Code can be used directly, has been verified)
Platform: | Size: 195584 | Author: kelvinlu | Hits:

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[USB develop] USB2.0_rtl_ipcore_verilog

[Other resource] USB2.0IP_core_Verilog

[USB develop] usb_funct

[VHDL-FPGA-Verilog] USB2.0 IP核

[USB develop] USB2_chip

[VHDL-FPGA-Verilog] USB2.0IP_core_Verilog

[VHDL-FPGA-Verilog] usb_funct[1].tar

[USB develop] usb_funct

[Software Engineering] WNUSB

[VHDL-FPGA-Verilog] USB2.0IP

[Software Engineering] USB_IP

[VHDL-FPGA-Verilog] VERILOG-USB2.0IP-core

[Software Engineering] USB2.0DeviceControllerIPCoreDesignandVerification.

[VHDL-FPGA-Verilog] USB2.0IP(RTL)

[VHDL-FPGA-Verilog] USB2.0-IP-core

[VHDL-FPGA-Verilog] verilog-usb--protel-design

[VHDL-FPGA-Verilog] USB2.0-IP

[VHDL-FPGA-Verilog] USB2.0IP

[VHDL-FPGA-Verilog] USB2.0IPcoredesign

[VHDL-FPGA-Verilog] USB2.0的IP核（详细verilog源码和文档）

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