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Title: USB2.0IP Download
 Description: Complete Verilog language developed by USB2.0 IP core source code, including documentation
 Downloaders recently: [More information of uploader chenrun1986]
  • [DW8051_2] - DW8051 High-Speed 8051 IP Core, I tested
  • [fifo-ram] - Verilog language used to describe the FI
  • [USB2.0] - usb+ fpga development board schematics,
  • [USB] -
  • [usb20_ipcore_usb_funct] - usb chips ip core. with HDL description
  • [can] - can IP CORE. VERY GOOD AS A STUDY FILE
File list (Check if you may need any files):
USB2.0的IP核,包含文档和Verilog源码
...................................\usb_funct
...................................\.........\bench
...................................\.........\.....\CVS
...................................\.........\.....\...\Entries
...................................\.........\.....\...\Repository
...................................\.........\.....\...\Root
...................................\.........\.....\verilog
...................................\.........\.....\.......\CVS
...................................\.........\.....\.......\...\Entries
...................................\.........\.....\.......\...\Repository
...................................\.........\.....\.......\...\Root
...................................\.........\doc
...................................\.........\...\CVS
...................................\.........\...\...\Entries
...................................\.........\...\...\Repository
...................................\.........\...\...\Root
...................................\.........\...\README.txt
...................................\.........\...\STATUS.txt
...................................\.........\...\usb_doc.pdf
...................................\.........\rtl
...................................\.........\...\CVS
...................................\.........\...\...\Entries
...................................\.........\...\...\Repository
...................................\.........\...\...\Root
...................................\.........\...\verilog
...................................\.........\...\.......\CVS
...................................\.........\...\.......\...\Entries
...................................\.........\...\.......\...\Repository
...................................\.........\...\.......\...\Root
...................................\.........\...\.......\usbf_crc16.v
...................................\.........\...\.......\usbf_crc5.v
...................................\.........\...\.......\usbf_defines.v
...................................\.........\...\.......\usbf_ep_rf.v
...................................\.........\...\.......\usbf_ep_rf_dummy.v
...................................\.........\...\.......\usbf_idma.v
...................................\.........\...\.......\usbf_mem_arb.v
...................................\.........\...\.......\usbf_pa.v
...................................\.........\...\.......\usbf_pd.v
...................................\.........\...\.......\usbf_pe.v
...................................\.........\...\.......\usbf_pl.v
...................................\.........\...\.......\usbf_rf.v
...................................\.........\...\.......\usbf_top.v
...................................\.........\...\.......\usbf_utmi_if.v
...................................\.........\...\.......\usbf_utmi_ls.v
...................................\.........\...\.......\usbf_wb.v
...................................\.........\sim
...................................\.........\...\CVS
...................................\.........\...\...\Entries
...................................\.........\...\...\Repository
...................................\.........\...\...\Root
...................................\.........\...\rtl_sim
...................................\.........\...\.......\bin
...................................\.........\...\.......\...\CVS
...................................\.........\...\.......\...\...\Entries
...................................\.........\...\.......\...\...\Repository
...................................\.........\...\.......\...\...\Root
...................................\.........\...\.......\CVS
...................................\.........\...\.......\...\Entries
...................................\.........\...\.......\...\Repository
...................................\.........\...\.......\...\Root
...................................\.........\...\.......\run
...................................\.........\...\.......\...\CVS
...................................\.........\...\....

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