Description: usb2.0 IP core for FPGA design of the USB interface communication, more flexible control interface hardware.
Detailed USB2.0 protocol description
To Search:
File list (Check if you may need any files):
USB2.0的IP核（详细verilog源码和文档）\usb_funct\bench\CVS\Entries
.....................................\.........\.....\...\Repository
.....................................\.........\.....\...\Root
.....................................\.........\.....\verilog\CVS\Entries
.....................................\.........\.....\.......\...\Repository
.....................................\.........\.....\.......\...\Root
.....................................\.........\doc\CVS\Entries
.....................................\.........\...\...\Repository
.....................................\.........\...\...\Root
.....................................\.........\...\README.txt
.....................................\.........\...\STATUS.txt
.....................................\.........\...\usb_doc.pdf
.....................................\.........\rtl\CVS\Entries
.....................................\.........\...\...\Repository
.....................................\.........\...\...\Root
.....................................\.........\...\verilog\CVS\Entries
.....................................\.........\...\.......\...\Repository
.....................................\.........\...\.......\...\Root
.....................................\.........\...\.......\usbf_crc16.v
.....................................\.........\...\.......\usbf_crc5.v
.....................................\.........\...\.......\usbf_defines.v
.....................................\.........\...\.......\usbf_ep_rf.v
.....................................\.........\...\.......\usbf_ep_rf_dummy.v
.....................................\.........\...\.......\usbf_idma.v
.....................................\.........\...\.......\usbf_mem_arb.v
.....................................\.........\...\.......\usbf_pa.v
.....................................\.........\...\.......\usbf_pd.v
.....................................\.........\...\.......\usbf_pe.v
.....................................\.........\...\.......\usbf_pl.v
.....................................\.........\...\.......\usbf_rf.v
.....................................\.........\...\.......\usbf_top.v
.....................................\.........\...\.......\usbf_utmi_if.v
.....................................\.........\...\.......\usbf_utmi_ls.v
.....................................\.........\...\.......\usbf_wb.v
.....................................\.........\sim\CVS\Entries
.....................................\.........\...\...\Repository
.....................................\.........\...\...\Root
.....................................\.........\...\rtl_sim\bin\CVS\Entries
.....................................\.........\...\.......\...\...\Repository
.....................................\.........\...\.......\...\...\Root
.....................................\.........\...\.......\CVS\Entries
.....................................\.........\...\.......\...\Repository
.....................................\.........\...\.......\...\Root
.....................................\.........\...\.......\run\CVS\Entries
.....................................\.........\...\.......\...\...\Repository
.....................................\.........\...\.......\...\...\Root
.....................................\.........\.yn\bin\comp.dc
.....................................\.........\...\...\CVS\Entries
.....................................\.........\...\...\...\Repository
.....................................\.........\...\...\...\Root
.....................................\.........\...\...\design_spec.dc
.....................................\.........\...\...\lib_spec.dc
.....................................\.........\...\...\read.dc
.....................................\.........\...\CVS\Entries
.....................................\.........\...\...\Repository
.....................................\.........\...\...\Root
.....................................\.........\...\log\CVS\Entries
.....................................\.........\...\...\...\Repository
.....................................\.........\...\...\
Download