Search - DDS vhdl code

[VHDL-FPGA-Verilog] FPGA_SUM99_VHDL_SOURCE

Description: 基于FPGA的直接数字合成器的设计与分析的代码程序,代码格式为VHDL-FPGA-based Direct Digital Synthesis Design and Analysis of the code procedures for VHDL code format
Platform: | Size: 5120 | Author: 莫汉伟 | Hits:

[VHDL-FPGA-Verilog] dds_quicklogic

Description: 高手写的VHDL源码，实现DDS跳频器功能请大家多提意见-experts write VHDL source code, the frequency-hopping DDS functionality Please speak up
Platform: | Size: 25600 | Author: duyi | Hits:

[VHDL-FPGA-Verilog] ddsmatlab

Description: dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-dds dspbuilder under the VHDL source code and test incentives document matl ab model, the simulation under through modelsim
Platform: | Size: 6144 | Author: zqh | Hits:

[VHDL-FPGA-Verilog] DDSsingal

Description: 三相直接数字频率合成器dds的VHDL源码，希望对大家有帮助-three-phase direct digital frequency synthesizers dds VHDL source code, we hope to help
Platform: | Size: 17408 | Author: xingyang | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 用51和 FPGA实现的 DDS的程序-FPGA with 51 and realize the process of DDS
Platform: | Size: 5120 | Author: 胡玉贵 | Hits:

[Communication-Mobile] DDS

Description: DDS的VHDL源代码，是数字QPSK调制解调中的重要组成部分。-DDS of the VHDL source code, the number of QPSK modulation and demodulation is an important part.
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 一个直接数字频率合成的查表程序,VHDL语言,使用7128调试通过-A direct digital frequency synthesis of look-up table procedures, VHDL language, using 7128 debugging through
Platform: | Size: 147456 | Author: Chen.Y.M | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: vhdl的一些源代码，包括dds 设计，交通灯设计，信号发生器设计的一些源代码-Some of VHDL source code, including dds design, traffic signal design, signal generator designed a number of source code
Platform: | Size: 70656 | Author: 马斌 | Hits:

[VHDL-FPGA-Verilog] dds

Description: DDs直接数字频率合成器的源代码，其中包括采用IP核和普通两种方式-DDS Direct Digital Synthesizer source code, including the use of IP core and the general two ways
Platform: | Size: 1378304 | Author: 谭儆轩 | Hits:

[Embeded-SCM Develop] 200741691252

Description: dds源代码，vhdl程序，函数信号发生器。-dds source code, vhdl procedure, function signal generator.
Platform: | Size: 4096 | Author: 吴飞 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 使用VHDL硬件描述语言实现了直接频率合成器的制作，并在Altera公司的CycloneII上得到实现，验证了代码的正确性。用户操作可以参照程序中的说明，请使用QuartusII6.0以上版本打开，低版本打开时会有错误提示-Using VHDL hardware description language to achieve a direct frequency synthesizer production, and Altera s CycloneII be realized, to verify the correctness of the code. Users can refer to procedures, please use the above QuartusII6.0 open, low-version will be opened error
Platform: | Size: 105472 | Author: xx | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 实现函数波形发生器的功能，内有用自己编的源代码实现的，也有用quartus的IP核实现的。-The realization of the function waveform generator function, useful for their own realization of the source code, it also uses the IP core quartus achieved.
Platform: | Size: 1251328 | Author: bluesky428 | Hits:

[VHDL-FPGA-Verilog] FPGA-DDS

Description: 在FPGA内，以查表方式实现频率直接合成器（DDS）功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
Platform: | Size: 2048 | Author: niuqs | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 本代码可以用于产生正余弦信号波形，利用FPGA内部的ROM放置一个正余弦采样点的数据表格，通过循环取址的方法，实现波形连续输出。-This code can be used to generate positive cosine signal waveforms, using FPGA' s internal ROM to place a sampling point is the cosine of the data tables, the circulation method of taking the site to achieve a continuous output waveform.
Platform: | Size: 484352 | Author: 蔡野锋 | Hits:

[Other] DDS

Description: 这个一个基于FPGA的DDS原代码可以生成正弦和余弦两种波形-This is a DDS code bepend on FPGA ,it can generate two waves.
Platform: | Size: 9216 | Author: wuyanjun | Hits:

[VHDL-FPGA-Verilog] 8psk

Description: 利用DDS原理设计8psk的原代码，已通过调试-8psk principle design using DDS source code, which has passed the commissioning
Platform: | Size: 1807360 | Author: luyuan | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS数字频率合成的verilog代码，附有正余弦查找表等-DDS digital frequency synthesis verilog code, with a cosine look-up table, etc.
Platform: | Size: 16772096 | Author: allen-haha | Hits:

[VHDL-FPGA-Verilog] singnal

Description: VHDL实现通用通信信号源，包括sin，cos，方波，三角波，BPSK，GMSK，ASK，16QAM等信号的产生以及DDS，PLL的VHDL系统代码-VHDL implementation of universal communication sources, including sin, cos, square, triangle, BPSK, GMSK, ASK, 16QAM and other signal generation and DDS, PLL system, the VHDL code
Platform: | Size: 1024 | Author: 张泽端 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 这个是在quartusii和matlab simulink下搭的dds的模型，已经经过仿真是可以的。并且已经转为vhdl代码。-This is quartusii and matlab simulink model to catch the dds, has been the simulation is possible. And has to vhdl code.
Platform: | Size: 1288192 | Author: jiang | Hits:

[VHDL-FPGA-Verilog] dds

Description: VHDL的DDS代码，也就是直接数字式频率合成器设计-The DDS VHDL code, which is Direct Digital Frequency Synthesizer
Platform: | Size: 3072 | Author: quanguoxiang | Hits:

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[VHDL-FPGA-Verilog] FPGA_SUM99_VHDL_SOURCE

[VHDL-FPGA-Verilog] dds_quicklogic

[VHDL-FPGA-Verilog] ddsmatlab

[VHDL-FPGA-Verilog] DDSsingal

[VHDL-FPGA-Verilog] DDS

[Communication-Mobile] DDS

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] dds

[Embeded-SCM Develop] 200741691252

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] FPGA-DDS

[VHDL-FPGA-Verilog] DDS

[Other] DDS

[VHDL-FPGA-Verilog] 8psk

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] singnal

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

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