Search - DDS PLL

[Communication-Mobile] DDS+PLL

Description: 基于FPGA的新的DDS+PLL时钟发生器-FPGA-based new DDS PLL clock generator
Platform: | Size: 145605 | Author: 李敏 | Hits:

[Other resource] DDSPLL

Description: 无线传送,DDS PLL 在频率合成中的应用,经典文章.-wireless transmission, DDS PLL frequency synthesizer in the application of classic articles.
Platform: | Size: 89030 | Author: king | Hits:

[SourceCode] 控制DDS与PLL程序

Description: 本程序用于控制DDS9912和AD4106工作的串口程序
Platform: | Size: 10053 | Author: 125697749@qq.com | Hits:

[Communication-Mobile] DDS+PLL

Description: 基于FPGA的新的DDS+PLL时钟发生器-FPGA-based new DDS PLL clock generator
Platform: | Size: 145408 | Author: 李敏 | Hits:

[OS Develop] MC145163PDDS

Description: MC145163P型锁相频率合成器的原理与应用-MC145163P- PLL frequency synthesizer and application of the principle
Platform: | Size: 339968 | Author: | Hits:

[Communication-Mobile] EXPT12_10_PHAS_PLL1

Description: VHDL 实现DDS的数字移相信号发生器的设计代码.直接解压打开就可以运行..自己写的代码-VHDL shifter DDS signal generator design code. Directly extract can run on open .. write their own code
Platform: | Size: 119808 | Author: haiou | Hits:

[Other] DDSPLL

Description: 无线传送,DDS PLL 在频率合成中的应用,经典文章.-wireless transmission, DDS PLL frequency synthesizer in the application of classic articles.
Platform: | Size: 89088 | Author: king | Hits:

[Program doc] DDS

Description: FPGA中实现基于查找表方式（LUT）的DDS实现，可用在数字下变频和COSTAS锁相环中，Verilog编写，本人已经调通-In FPGA-based lookup table approach (LUT) to achieve the DDS can be used in the digital down-conversion and COSTAS PLL, Verilog prepared, I have transferred Qualcomm
Platform: | Size: 148480 | Author: | Hits:

[SCM] sgs32

Description: Verlog HDL 写得一款32路方波发生器，例子是4路可以自己加，相位可调，频率可调，占空比可调。具体参见readme.doc.此处只提供了源码包含顶层模块sgs32.v 子模块dds.v和pll设置模块altp.v及波形驱动文件-Verlog HDL write a 32 square-wave generator, for example, is able to add 4-way, phase adjustable, adjustable frequency, adjustable duty cycle. See readme.doc. Here only provide a source module that contains the top-level sub-modules sgs32.v settings dds.v and pll module altp.v and waveform-driven document
Platform: | Size: 59392 | Author: TTHR | Hits:

[VHDL-FPGA-Verilog] dds_new

Description: 驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率可以做到Hz量级-Clock driver joined the PLL, the DDS makes the clock-driven variable-.32-bit NCO makes the resolution of DDS can be done Hz magnitude
Platform: | Size: 2024448 | Author: 李春剑 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
Platform: | Size: 190464 | Author: 赵一 | Hits:

[Technology Management] dds9851

Description: 本文主要介绍的是采用直接数字频率合成的短波信号发生器，它主要以微电脑控制部分、直接数字频率合成（DDS）部分、数字锁相环频率合成部分、背光液晶显示部分、功率放大部分等组成。该软件系统采用菜单形式进行操作，操作方便明了，增加了很多功能。它通过启动DDS后，把内存缓存区的数据送到DDS后输出相应的频率，并把数据转换为BCD码，送到液晶显示器进行显示。该系统输出稳定度、精度极高，适用于当代的尖端的通信系统和精密的高精度仪器。-This paper describes the use of direct digital frequency synthesis of short-wave signal generator, which is part of a micro-computer control, Direct Digital Synthesis (DDS) of the digital part of PLL frequency synthesizer, backlit liquid crystal display of the power amplifier, etc. composition. The menu system uses the form of software to operate, easy to operate and clear, increase in the number of features. DDS through start after the memory cache after the data to the DDS output corresponding frequency, and the data is converted to BCD code to the LCD display. The output of the system stability, high precision for cutting-edge contemporary and sophisticated communication systems high-precision instruments
Platform: | Size: 466944 | Author: xiang | Hits:

[SCM] dfefe.doc

Description: 该高频正弦信号发生器基于直接数字频率合成（DDS）和数字锁相环技术（DPLL），以微控制器（MCU）和现场可编程逻辑门阵列（FPGA）为核心，辅以必要的外围电路设计而成。系统主要由正弦信号发生、红外遥控、高速模数（A/D）－数模（D/A）转换、信号调制和后级处理等模块组成。-The high-frequency sinusoidal signal generator based on Direct Digital Synthesis (DDS) and digital PLL (DPLL), a microcontroller (MCU) and field programmable gate array (FPGA) as the core, supplemented by the necessary peripheral from circuit design. System is composed of sinusoidal signal, infrared remote control, high-speed module (A/D)- digital-analog (D/A) conversion, signal modulation and post-level processing modules.
Platform: | Size: 243712 | Author: henry | Hits:

[Other] 10.1.1.19.9992

Description: complete project design for pll and dds
Platform: | Size: 66560 | Author: johngrivas | Hits:

[VHDL-FPGA-Verilog] singnal

Description: VHDL实现通用通信信号源，包括sin，cos，方波，三角波，BPSK，GMSK，ASK，16QAM等信号的产生以及DDS，PLL的VHDL系统代码-VHDL implementation of universal communication sources, including sin, cos, square, triangle, BPSK, GMSK, ASK, 16QAM and other signal generation and DDS, PLL system, the VHDL code
Platform: | Size: 1024 | Author: 张泽端 | Hits:

[VHDL-FPGA-Verilog] FDDDDSPLLP

Description: 一种基于FPGA的新的的DDS+PLL时钟发生器 -An FPGA-based new DDS+PLL clock generator
Platform: | Size: 145408 | Author: 房产 | Hits:

[Other] Pro_19

Description: Fpga,DDS,PLL,rom(正弦波)(f<13MHz,需要滤波)(Verilog)-Fpga, DDS, PLL, rom
Platform: | Size: 630784 | Author: 夏九星 | Hits:

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[Communication-Mobile] DDS+PLL

[Other resource] DDSPLL

[SourceCode] 控制DDS与PLL程序

[Communication-Mobile] DDS+PLL

[OS Develop] MC145163PDDS

[Communication-Mobile] EXPT12_10_PHAS_PLL1

[Other] DDSPLL

[Program doc] DDS

[SCM] sgs32

[VHDL-FPGA-Verilog] dds_new

[VHDL-FPGA-Verilog] dds

[Technology Management] dds9851

[SCM] dfefe.doc

[Other] 10.1.1.19.9992

[VHDL-FPGA-Verilog] singnal

[VHDL-FPGA-Verilog] FDDDDSPLLP

[Other] Pro_19

[Other Embeded program] FFT-sampling-and-analysis

[Software Engineering] dds-pll

[Communication-Mobile] dds_AD9834+rw

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