Description: Clock driver joined the PLL, the DDS makes the clock-driven variable-.32-bit NCO makes the resolution of DDS can be done Hz magnitude
- [dds] - Direct digital frequency synthesizer, ba
- [11] - Verilog arbitrary-dimensional matrix inv
- [ref-ddr-sdram-vhdl] - VHDL prepared based on the DDR-SDRAM con
File list (Check if you may need any files):
dds_new
.......\acc.bsf
.......\acc.v
.......\acc1.bsf
.......\acc1.v
.......\acc1_bb.v
.......\acc1_waveforms.html
.......\acc2.bsf
.......\acc2.v
.......\acc2_bb.v
.......\acc2_waveforms.html
.......\acc_bb.v
.......\acc_clk.bsf
.......\acc_clk.v
.......\acc_clk_bb.v
.......\acc_clk_waveforms.html
.......\acc_waveforms.html
.......\add.bsf
.......\add.v
.......\add0.bsf
.......\add0.v
.......\add0_bb.v
.......\add0_waveforms.html
.......\adder.bsf
.......\adder.v
.......\adder_bb.v
.......\adder_wave0.jpg
.......\adder_waveforms.html
.......\add_bb.v
.......\add_wave0.jpg
.......\add_waveforms.html
.......\db
.......\..\add_sub_0pe.tdf
.......\..\add_sub_omg.tdf
.......\..\add_sub_q4h.tdf
.......\..\altsyncram_5071.tdf
.......\..\dds_new.asm.qmsg
.......\..\dds_new.asm_labs.ddb
.......\..\dds_new.cbx.xml
.......\..\dds_new.cmp.bpm
.......\..\dds_new.cmp.cdb
.......\..\dds_new.cmp.ecobp
.......\..\dds_new.cmp.hdb
.......\..\dds_new.cmp.logdb
.......\..\dds_new.cmp.rdb
.......\..\dds_new.cmp.tdb
.......\..\dds_new.cmp0.ddb
.......\..\dds_new.cmp_bb.cdb
.......\..\dds_new.cmp_bb.hdb
.......\..\dds_new.cmp_bb.logdb
.......\..\dds_new.cmp_bb.rcf
.......\..\dds_new.dbp
.......\..\dds_new.db_info
.......\..\dds_new.eco.cdb
.......\..\dds_new.eds_overflow
.......\..\dds_new.fit.qmsg
.......\..\dds_new.fnsim.cdb
.......\..\dds_new.fnsim.hdb
.......\..\dds_new.fnsim.qmsg
.......\..\dds_new.hier_info
.......\..\dds_new.hif
.......\..\dds_new.map.bpm
.......\..\dds_new.map.cdb
.......\..\dds_new.map.ecobp
.......\..\dds_new.map.hdb
.......\..\dds_new.map.logdb
.......\..\dds_new.map.qmsg
.......\..\dds_new.map_bb.cdb
.......\..\dds_new.map_bb.hdb
.......\..\dds_new.map_bb.logdb
.......\..\dds_new.merge_hb.atm
.......\..\dds_new.pre_map.cdb
.......\..\dds_new.pre_map.hdb
.......\..\dds_new.psp
.......\..\dds_new.pss
.......\..\dds_new.rtlv.hdb
.......\..\dds_new.rtlv_sg.cdb
.......\..\dds_new.rtlv_sg_swap.cdb
.......\..\dds_new.sgdiff.cdb
.......\..\dds_new.sgdiff.hdb
.......\..\dds_new.signalprobe.cdb
.......\..\dds_new.sim.cvwf
.......\..\dds_new.sim.hdb
.......\..\dds_new.sim.qmsg
.......\..\dds_new.sim.rdb
.......\..\dds_new.simfam
.......\..\dds_new.sld_design_entry.sci
.......\..\dds_new.sld_design_entry_dsc.sci
.......\..\dds_new.syn_hier_info
.......\..\dds_new.tan.qmsg
.......\..\dds_new.tis_db_list.ddb
.......\..\decode_4oa.tdf
.......\..\mux_vjb.tdf
.......\..\prev_cmp_dds_new.asm.qmsg
.......\..\prev_cmp_dds_new.fit.qmsg
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