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[Documents] 异步FIFO结构及FPGA设计 DL : 0: 介绍异步FIFO的概念、应用及其结构，分析实现异步FIFO的难点问题及其解决办法；在传统设计的基础上提出一种新颖的电路结构并对其进行综合仿真和FPGA实现。
Date : 2009-05-06 Size : 166kb User : sht816dzkd@163.com
[Documents] sci 列阵 DL : 0: 功能介绍： DSP2812 SCI 串口模块，利用队列来完成软件FIFO,实现数据缓冲,提高数据的利用效率。
Date : 2010-06-23 Size : 72.5kb User : 6525231@sina.com
[Documents] asychronous_fifo_design_cummings DL : 0: fifo的重要文章，非常经典，cummings的两篇再加上一些其他的，读过不后悔-fifo the important articles, very classic, the two cummings with some other, read no regrets
Date : 2025-12-21 Size : 465kb User : 梦梦
[Documents] osp1 DL : 0: 内存管理的四种页面置换算法 FIFO LRU NUR OPT-Memory management page replacement algorithm for the four FIFO LRU NUR OPT
Date : 2025-12-21 Size : 218kb User : 子小
[Documents] NewMsg-RF1100 DL : 0: (1) 315、433、868、915Mh的ISM 和SRD频段 (2) 最高工作速率500kbps，支持2-FSK、GFSK和MSK调制方式 (3) 高灵敏度（1.2kbps下-110dDm，1％数据包误码率） (4) 内置硬件CRC 检错和点对多点通信地址控制 (5) 较低的电流消耗（RX中，15.6mA，2.4kbps,433MHz） (6) 可编程控制的输出功率，对所有的支持频率可达+10dBm (7) 支持低功率电磁波激活功能 (8) 支持传输前自动清理信道访问（CCA），即载波侦听系统 (9) 快速频率变动合成器带来的合适的频率跳跃系统 (10) 模块可软件设地址，软件编程非常方便 (11) 标准DIP间距接口，便于嵌入式应用 (12) 单独的64字节RX和TX数据FIFO-(1) 315,433,868,915 Mh of the ISM and SRD frequency bands (2) maximum rate of 500kbps, support for 2-FSK, GFSK and MSK modulation (3) high sensitivity (1.2kbps under-110dDm, 1 packet error bit-rate) (4) built-in hardware CRC error detection and control of point-to-multipoint communication address (5) a lower current consumption (RX in, 15.6mA, 2.4kbps, 433MHz) (6) programmable control of output power for all the support frequencies up to+ 10dBm (7) to support low-power electromagnetic wave activation (8) to support the transmission before the automatic clean-up Channel Access (CCA), namely Carrier Sense System (9) Fast frequency synthesizer brought about by changes in suitable frequency hopping system (10) modules can be software-based address, software programming is easy (11) standard DIP spacing interfaces for embedded applications (12) separate 64-byte RX and TX data FIFO
Date : 2025-12-21 Size : 312kb User : 李华力
[Documents] shiyan DL : 0: 利用队列的先进先出特性解决火车重排问题，输入车厢长度及顺序编号后由程序自动完成排列-Characteristics of the use of FIFO queues to solve the train rearrangement problem, enter the compartment length and serial numbers automatically after the completion of arrangement
Date : 2025-12-21 Size : 221kb User : silver
[Documents] jincheng DL : 0: 进程调度模拟程序:假设有10个进程需要在CPU上执行,分别用:先进先出调度算法基于优先数的调度算法最短执行时间调度算法确定这10个进程在CPU上的执行过程.要求每次进程调度时在屏幕上显示:当前执行进程就绪队列等待队列-Process scheduling simulation program: Suppose there are 10 process requires the CPU to perform, respectively: FIFO scheduling algorithm the number of priority-based scheduling algorithms the shortest execution time scheduling algorithm to determine the 10 process CPU on the implementation process. Requirements Every time the process of scheduling, when displayed on the screen: the current implementation process ready queue waiting queue
Date : 2025-12-21 Size : 580kb User : lienquan
[Documents] 12 DL : 0: 操作系统课程设计，课程设计得优，FIFO,LRU,等算法的实现-Operating system program design, program designed to excellent, FIFO, LRU, etc. Algorithm
Date : 2025-12-21 Size : 2kb User : dandan
[Documents] FIFO DL : 0: FIFO设计所必须要看的，关于FIFO参数的介绍-FIFO design must depend on, and on the FIFO parameters introduced
Date : 2025-12-21 Size : 19kb User : yeyueyue
[Documents] fifo_verilog DL : 0: fifo的设计代码。可以运行和仿真。可以作为参考之用-fifo design code. Run
Date : 2025-12-21 Size : 180kb User : yeyueyue
[Documents] FIFO-[Compatibility-Mode] DL : 0: fifo specification for designing verilog
Date : 2025-12-21 Size : 522kb User : ram
[Documents] OV7670new DL : 0: documents for cammera with al422b fifo memory data
Date : 2025-12-21 Size : 1.07mb User : req