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[Software Engineering] 68013_slave_FIFO DL : 0: 关于FIFO的一些设计资料，共享！欢迎更多的资料共享！-FIFO on the design of some information sharing! Welcome more information sharing!
Date : 2025-12-21 Size : 253kb User : yqs6632
[Software Engineering] design-flow-speeding-up-dsp DL : 0: Wavelets have widely been used in many signal and image processing applications. In this paper, a new serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet transform, which is realised using some FIFO memory modules implementing a pixel-level pipeline architecture to compress and decompress images. The real filter calculation over 4 · 4 window blocks is done using a tree of carry save adders to ensure the high speed processing required for many applications. The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis reveals that the proposed architecture, implemented using current VLSI technologies, can process a video stream in real time.-Wavelets have been widely used in many sign al and image processing applications. In this p aper. a new serial-parallel architecture for wavele t-based image compression is introduced. It is based on a 4-tap wavelet transform. which is realized using some FIFO memory module 's implementing a pixel-level pipeline archite cture to compress and decompress images. The're al filter calculation over 4 blocks window is done using a tree of carry save adders to ensure t he high speed processing required for many appl ications. The details of implementing both com pressor decompressor and sub-systems are give n. The primarily analysis reveals that the prop osed architecture, VLSI implemented using current technologies, can process a video stream in real time.
Date : 2025-12-21 Size : 2.71mb User : sdfafaf
[Software Engineering] fifo1.pdf DL : 0: 提出了利用fifo,实现dsp之间的高速、实时、可靠的数据传输,介绍了fifo原理及性能特点，详细阐述了系统的硬件接口电路及软件设计。 -the use fifo achieve dsp between the high-speed, real-time, reliable data transmission, fifo on the principles and performance characteristics of a detailed description of the hardware and software interface circuit design.
Date : 2025-12-21 Size : 85kb User : 权溪
[Software Engineering] fifo3.pdf DL : 0: 重点介绍了DSP与FIFO的数据传输、DSP与USB的接口电路。解决了一般情况下系统无法做到的用线阵CCD实现二维图像信号复原的问题 -focus on the DSP and FIFO data transmission, DSP and USB interface circuit. Solve the system under normal circumstances can not do in line with two-dimensional CCD image signals of recovery
Date : 2025-12-21 Size : 131kb User : 权溪
[Software Engineering] fifo_generator_ug175 DL : 0: 该文档是有关利用XINLIX的FPGA如何实现FIFO的生成及如何应用的文章。-The document is related to the FPGA using XINLIX how to achieve FIFO generation and how to use the article.
Date : 2025-12-21 Size : 698kb User : cobain
[Software Engineering] CummingsSNUG2002SJ_FIFO1 DL : 1: 此项是针对设计异步FIFO的比较好的一个文档，共两篇，这是第一篇。-The asynchronous FIFO design for the relatively good a document, a total of 2, this is the first.
Date : 2025-12-21 Size : 117kb User : 王辉
[Software Engineering] CummingsSNUG2002SJ_FIFO2 DL : 0: 此项是针对设计异步FIFO的比较好的一个文档，共两篇，这是第二篇。
Date : 2025-12-21 Size : 99kb User : 王辉
[Software Engineering] asynchronous_FIFO_01to03_CHN DL : 0: 这是设计异步FIFO的比较好的一个参考资料，希望可以对大家有用。-This is the design of better asynchronous FIFO a reference, I hope can be useful to everyone.
Date : 2025-12-21 Size : 533kb User : 王辉
[Software Engineering] Asyn_FIFO_Design DL : 0: 异步FIFO设计的说明文档，需要注意的问题以及源码（在文中有）。是标准的异步FIFO，可综合。-Asynchronous FIFO design documentation, as well as the need to pay attention to source code (in the text have). Is a standard asynchronous FIFO, can be integrated.
Date : 2025-12-21 Size : 223kb User : 刘强
[Software Engineering] multiplier_8bit DL : 0: 异步FIFO设计的说明文档，需要注意的问题以及源码（在文中有）。是标准的异步FIFO，可综合。-Asynchronous FIFO design documentation, as well as the need to pay attention to source code (in the text have). Is a standard asynchronous FIFO, can be integrated.
Date : 2025-12-21 Size : 45kb User : 刘强
[Software Engineering] labQ2 DL : 0: Source codes for verilog fifo for spartan 3
Date : 2025-12-21 Size : 247kb User : Krishna
[Software Engineering] CummingsSNUG2002SJ_FIFO2 DL : 0: Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons
Date : 2025-12-21 Size : 99kb User : sumit
[Software Engineering] fifo DL : 1: 异步fifo的经典讲解，包括亚稳态的产生，同步电路的构造，fifo电路的结构，源代码实现。-Asynchronous fifo on the classic, including the emergence of metastable, the structure of synchronous circuits, fifo circuit structure, the source code to achieve.
Date : 2025-12-21 Size : 3.08mb User : 王玉
[Software Engineering] AsynchronousFIFOArchitectures-CN DL : 0: AsynchronousFIFOArchitectures，这篇经典FPGA-FIFO文章的中文版-AsynchronousFIFOArchitectures, this classic FPGA-FIFO Chinese version of the article
Date : 2025-12-21 Size : 533kb User : energy
[Software Engineering] ASY_FIFO DL : 0: 异步FIFO的设计,对整个异步FIFO的过程进行了详细的介绍-the design of the asy FIFO
Date : 2025-12-21 Size : 94kb User : isaac
[Software Engineering] FIFO DL : 0: 針對作業系統原理所做得FIFO的PAGEFAULT可顯示分頁錯誤次數-Principles for the operating system by doing FIFO, PAGEFAULT the number of errors can be displayed page
Date : 2025-12-21 Size : 1kb User : your name
[Software Engineering] fifo DL : 0: this verilog program for sysnchronous FIFO ,this document contains some error using before correct and then use,-this is verilog program for sysnchronous FIFO ,this document contains some error using before correct and then use,
Date : 2025-12-21 Size : 34kb User : toyanath
[Software Engineering] source_code DL : 0: verilog code fifo memory usb
Date : 2025-12-21 Size : 4kb User : mohsen
[Software Engineering] FIFO DL : 0: FIFO(first in first out) design written in Verilog
Date : 2025-12-21 Size : 1kb User : binh
[Software Engineering] generic_fifos DL : 0: Generic FIFO for use with both xilinx and altera
Date : 2025-12-21 Size : 39kb User : ufz

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