Asynchronous FIFO design documentation, as well as the need to pay attention to source code (in the text have). Is a standard asynchronous FIFO, can be integrated.

八位乘法器
..........\CHENGFA_8.asm.rpt
..........\CHENGFA_8.done
..........\CHENGFA_8.dpf
..........\CHENGFA_8.fit.rpt
..........\CHENGFA_8.fit.smsg
..........\CHENGFA_8.fit.summary
..........\CHENGFA_8.flow.rpt
..........\CHENGFA_8.map.rpt
..........\CHENGFA_8.map.summary
..........\CHENGFA_8.pin
..........\CHENGFA_8.qpf
..........\CHENGFA_8.qsf
..........\CHENGFA_8.qws
..........\CHENGFA_8.sim.rpt
..........\CHENGFA_8.tan.rpt
..........\CHENGFA_8.tan.summary
..........\CHENGFA_8.vhd
..........\CHENGFA_8.vwf
..........\CHENGFA_8_assignment_defaults.qdf
..........\cmp_state.ini
..........\db
..........\..\add_sub_3ph.tdf
..........\..\add_sub_3rh.tdf
..........\..\CHENGFA_8.db_info
..........\..\CHENGFA_8.eco.cdb
..........\..\CHENGFA_8.sld_design_entry.sci
..........\..\mux_jcc.tdf
..........\..\wed.zsf

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