Generic FIFO for use with both xilinx and altera

generic_fifos\bench\CVS\Entries
.............\.....\...\Repository
.............\.....\...\Root
.............\.....\verilog\CVS\Entries
.............\.....\.......\...\Repository
.............\.....\.......\...\Root
.............\.....\.......\test_bench_top.v
.............\CVS\Entries
.............\...\Repository
.............\...\Root
.............\doc\CVS\Entries
.............\...\...\Repository
.............\...\...\Root
.............\...\README.txt
.............\oc8051_dptr.v
.............\risc16f84_clk2x.v
.............\.tl\CVS\Entries
.............\...\...\Repository
.............\...\...\Root
.............\...\verilog\CVS\Entries
.............\...\.......\...\Repository
.............\...\.......\...\Root
.............\...\.......\generic_fifo_dc.v
.............\...\.......\generic_fifo_dc_gray.v
.............\...\.......\generic_fifo_lfsr.v
.............\...\.......\generic_fifo_sc_a.v
.............\...\.......\generic_fifo_sc_b.v
.............\...\.......\lfsr.v
.............\...\.......\timescale.v
.............\sim\CVS\Entries
.............\...\...\Repository
.............\...\...\Root
.............\...\rtl_sim\bin\CVS\Entries
.............\...\.......\...\...\Repository
.............\...\.......\...\...\Root
.............\...\.......\...\Makefile
.............\...\.......\CVS\Entries
.............\...\.......\...\Repository
.............\...\.......\...\Root
.............\...\.......\run\CVS\Entries
.............\...\.......\...\...\Repository
.............\...\.......\...\...\Root
.............\...\.......\...\waves\CVS\Entries
.............\...\.......\...\.....\...\Repository
.............\...\.......\...\.....\...\Root
.............\...\.......\...\.....\waves.do
.............\usb1_fifo2.v
.............\sim\rtl_sim\run\waves\CVS
.............\...\.......\bin\CVS
.............\...\.......\run\CVS
.............\...\.......\...\waves
.............\bench\verilog\CVS
.............\rtl\verilog\CVS
.............\sim\rtl_sim\bin
.............\...\.......\CVS
.............\...\.......\run
.............\bench\CVS
.............\.....\verilog
.............\doc\CVS
.............\rtl\CVS
.............\...\verilog
.............\sim\CVS
.............\...\rtl_sim
.............\bench
.............\CVS
.............\doc
.............\rtl
.............\sim
generic_fifos

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