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[Industry research] interfaces_for_mixed_timing_systems DL : 0: This paper presents several low-latency mixed-timing FIFO (first-in–first-out) interfaces designs that interface systems on a chip working at different speeds. The connected systems can be either synchronous or asynchronous. The designs are then adapted to work between systems with very long interconnect delays, by migrating a single-clock solution by Carloni et al. (1999, 2000, and 2001) (for “latency-insensitive” protocols) to mixed-timing domains. The new designs can be made arbitrarily robust with regard to metastability and interface operating speeds. Initial simulations for both latency and throughput are promising.-This paper presents several low-latency mixed-timingFIFO (first-in-first-out) interfaces designs that interface systemson a chip working at different speeds. The connected systemscan be either synchronous or asynchronous. The designs are thenadapted to work between systems with very long interconnectdelays, by migrating a single-clock solution by Carloni et al. (1999, 2000, and 2001) (for latency-insensitive protocols) tomixed-timing domains. The new designs can be made arbitrarilyrobust with regard to metastability and interface operating speeds.Initial simulations for both latency and throughput are promising.
Date : 2025-12-21 Size : 412kb User : 叶艳
[Industry research] Asynchronous-fifo-design DL : 0: Asynchronous fifo design
Date : 2025-12-21 Size : 118kb User : sandy
[Industry research] fifo DL : 0: fifo scheduling program
Date : 2025-12-21 Size : 71kb User : yagami