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[Other] booth DL : 0: -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check --- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check
Date : 2025-12-17 Size : 1kb User : leanne
[Other] PHR DL : 0: Lagrange乘子法用于解约束最优化问题 -Lagrange multiplier method for the solution of unconstrained optimization problem
Date : 2025-12-17 Size : 2kb User :
[Other] 8 DL : 0: 移位相加8位硬件乘法器电路设计乘法器是数字系统中的基本逻辑器件，在很多应用中都会出现如各种滤波器的设计、矩阵的运算等。本实验设计一个通用的8位乘法器。-Shift combined 8-bit hardware multiplier multiplier circuit design is a digital system in the basic logic devices, in many applications will emerge, and such a variety of filter design, such as matrix calculations. The experimental design of a generic 8-bit multiplier.
Date : 2025-12-17 Size : 5kb User : jun
[Other] UnsignMulti DL : 0: ALTERA上DE2平台，verilog描述，无符号乘法器，在数码管显示结果。-ALTERA on DE2 platform, verilog description unsigned multiplier, the result will be displayed in the digital pipe.
Date : 2025-12-17 Size : 858kb User : 徐朝凯
[Other] mul DL : 0: 加法器树乘法器结合了移位相加乘法器和查找表乘法器的优点。它使用的加法器数目等于操作数位数减 1 ，加法器精度为操作数位数的2倍，需要的与门数等于操作数的平方。因此 8 位乘法器需要7个15位加法器和64个与门-Adder tree multiplier multiplier combination of shift and add multiplier advantage of look-up table. It uses the adder operand is equivalent to the median minus 1, adder operand median accuracy of the 2-fold, and the gate count required operand equal to the square. 8-bit multiplier, therefore the need for 7 and 15 adder 64 and the door
Date : 2025-12-17 Size : 1kb User : 肖毅
[Other] MUL DL : 0: 8-bit modified Booth s algorithm multiplier
Date : 2025-12-17 Size : 79kb User : calvin
[Other] Parallel_Booth_Multiplier DL : 0: Parallel Booth Multiplier Circuit in VHDL
Date : 2025-12-17 Size : 11kb User : Carlos H Nacer
[Other] booth DL : 0: booth multiplier in verilog, deisgn in parameterized.
Date : 2025-12-17 Size : 25kb User : Udit
[Other] mult DL : 0: floating point multiplier
Date : 2025-12-17 Size : 2kb User : prashanthi
[Other] multiplier DL : 0: .v files for multiplier
Date : 2025-12-17 Size : 15kb User : Ifrah
[Other] Multiplier DL : 0: A multiplier unit in VHDL
Date : 2025-12-17 Size : 1kb User : Sonali
[Other] multiplier8x8 DL : 0: 8位定点乘法器，支持有符号数/无符号数运算。采用4-2压缩树结构，并提供testbench。-It is an 8-bit fixed-point multiplier, supporting signed/unsigned operations. Wallance tree structure with 4-2 compression. Provides testbench.
Date : 2025-12-17 Size : 2kb User : superbear
[Other] multiplier DL : 0: 增广乘子法，优化算法程序，采用Fortran语言编写-Augmented multiplier method, optimization procedures, using Fortran language
Date : 2025-12-17 Size : 1kb User : 张克
[Other] lagrange-multiplier DL : 0: Larange Multipliers-Larange Multipliers...........
Date : 2025-12-17 Size : 105kb User : moon
[Other] Multiplier DL : 0: 圖形介面乘法器,也可自行使用verilog去改-Graphical interface multiplier, also free to use verilog go and change
Date : 2025-12-17 Size : 221kb User : 具東白
[Other] 8bit-multiplier DL : 0: 8位二进制数乘法器VHDL实现8位二进制数乘法器设计，乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全0相加，直至被乘数的最高位。 -8-bit binary multiplier VHDL 8-bit binary multiplier design, multiplication by itemized shift sum principle, starting from the least significant bit of the multiplicand 1, the multiplier the left after the last and addition if it is 0, to 0 after adding the left until the most significant bit of the multiplicand.
Date : 2025-12-17 Size : 2kb User : 李谦
[Other] dcm-multiplier-routines- DL : 0: dcm倍频例程及其用法。包含完整的dcm工程文件。具体代码内容请下载查看-dcm multiplier routines and their usage. Dcm file contains the complete works. Please see the specific code download
Date : 2025-12-17 Size : 307kb User : wizz
[Other] Multiplier DL : 0: 我是2014级复旦的研究生。这是用VHDL语言设计的任意的M乘以N位的乘法器。设计中，被除数和乘数的位数是通过参数来设置的，可由你来修改。我已写好了testbench。可放心使用。-I am a 2014 graduate of Fudan University. This is an arbitrary M VHDL language designed by N-bit multiplier. Design, the dividend and the median multiplier is set by the parameter, you can modify. I have written a testbench. Ease of use.
Date : 2025-12-17 Size : 166kb User : ljt
[Other] Multiplier-method-program DL : 0: 优化算法，数学规划法，乘子法程序，MATLAB程序。-Multiplier method program
Date : 2025-12-17 Size : 3kb User : hyf
[Other] jeas_reversable-vedic-multiplier DL : 0: reversible logic is mainly used to achieve low power. peres gate HUG gate is used to design a vedic multiplier. reversible gate we can give n numbers of input and we can get n number of output
Date : 2025-12-17 Size : 544kb User : paramu

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