I am a 2014 graduate of Fudan University. This is an arbitrary M VHDL language designed by N-bit multiplier. Design, the dividend and the median multiplier is set by the parameter, you can modify. I have written a testbench. Ease of use.

MULTIPLIER\CODE
..........\....\bit_multiplier.vhd
..........\....\Multiplier_4x4.vhd
..........\....\Multiplier_4x4_sources.f
..........\....\Multiplier_4x4_tb.vhd
..........\....\Multiplier_NxM.vhd
..........\....\Multiplier_NxM_sources.f
..........\....\Multiplier_NxM_tb.vhd
..........\Title.pdf

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