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[Books] 一个并行高速乘法器芯片的设计与实现 DL : 0: 一个并行高速乘法器芯片的设计与实现-a parallel high-speed chip Multiplier Design and Implementation of
Date : 2025-12-16 Size : 32kb User : 虞亮
[Books] 32×32 DL : 0: 32×32乘法器的一种设计.pdf32×32乘法器的一种设计.pdf-32 × 32 multiplier of a design. Pdf32 × 32 multiplier of a design. Pdf
Date : 2025-12-16 Size : 246kb User :
[Books] AD9852CompleteDDSandItsApplication DL : 0: 摘要：AD9852是美国ANALOGDEVICES公司生产的新型直接数字频率合成器(DDS)，具有频率转换速度快(小于lt~s)、频谱纯度高、工作温度范围宽(一25℃～+85℃)、集成度高等特点，是一种使用方便灵活、功能较强的芯片。AD9852由带有48位相位累加的数控振荡器、可墒程参考时钟倍乘器、反向正弦滤波器、计数倍乘器、两个300MHz12住数模转换器、高速模拟比较器和接口逻辑组成。可用于本振合成回路，高精度时钟发生器和FSK／／3PSK调制。文中介绍了AD9852的工作原理、引脚功能以厦具体应用。 -Abstract: AD9852 is Analog Devices Inc. The United States produced a new type of direct digital synthesizers (DDS), with frequency conversion speed (less than lt ~ s), the spectrum of high purity, the working temperature range of width (1 25 ℃ ~+ 85 ℃) , high integration, is a flexible and easy to use, more powerful chips. AD9852 by a cumulative 48 DCO phase can be moisture-way Multiplier times the reference clock, reverse sine filter, multiplying count, two 300MHz12 live digital, high-speed analog comparator, and interface logic composition. Can be used in the synthesis loop vibration, high-precision clock generator and FSK// 3PSK modulation. This paper introduces the working principle of AD9852, pin functions to specific application of Xiamen.
Date : 2025-12-16 Size : 124kb User : 梅名
[Books] 32bits_float_muliplier DL : 0: 32位浮点乘法器的设计，讲的挺好的，供参考啊-32-bit floating-point multiplier design, speak very good, and for reference ah
Date : 2025-12-16 Size : 95kb User : downloader
[Books] 32bit DL : 0: model algorithm for 32 bit multiplier
Date : 2025-12-16 Size : 295kb User : damasqas
[Books] VHDL DL : 1: A gate level implementation of a Booth Encoded Radix-4 24 bit multiplier with VHDL code in structural form. Carry-save adder and hierarchical CLA adder is used for the component adders in the design. The 12 partial products is a Wallace Adder Tree built from Carry-save adder using 3 to 2 reduction. A hierarchical CLA ( Carry-look-Ahead Adder ) adder is used for the final product generation. -A gate level implementation of a Booth Encoded Radix-4 24 bit multiplier with VHDL code in structural form. Carry-save adder and hierarchical CLA adder is used for the component adders in the design. The 12 partial products is a Wallace Adder Tree built from Carry-save adder using 3 to 2 reduction. A hierarchical CLA ( Carry-look-Ahead Adder ) adder is used for the final product generation.
Date : 2025-12-16 Size : 7kb User : Michael Lee
[Books] wallace-functions DL : 0: wallace functions which is used for designing wallace tree for booth multiplier in vhdl
Date : 2025-12-16 Size : 1kb User : vichithra.uv
[Books] jspkc DL : 0: 基于VS2005 开发,结构简洁,配合动软Codematic代码生成器,可以使开发效率事半功倍...本系统主要功能 1,物品类别管理实现了物品类别的添加、修改、删除功能,方便库存... -Based on VS2005 development, simple structure, with dynamic soft Codematic code generator that allows development efficiency multiplier ... The main function of a system, goods category management to achieve the item category to add, modify, delete function to facilitate inventory ...
Date : 2025-12-16 Size : 751kb User : 邬兴华
[Books] New-folder-(2) DL : 0: project-IMPLEMENTATION OF FAST SDC-SDF PIPELINED FFT USING CSD MULTIPLIER
Date : 2025-12-16 Size : 820kb User : Gowri shankar