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[Other resource] 16位乘法器 DL : 0: 自已写的一个16X16的乘法器，速度比较慢。初学者练习练习！-own writing an audio Multiplier, speed is relatively slow. Beginners practice practice!
Date : 2008-10-13 Size : 1.97kb User : 唐勇翔
[Other resource] 8位相位相加乘法器 DL : 1: 8位相加乘法器，具有高速，占用资源较少的优点-eight multiplier phase together with high-speed, taking up less resources advantages
Date : 2008-10-13 Size : 4.69kb User : 张建
[Other resource] 51子程序库 DL : 0: 该文件里包含了大量的常用经典的程序代码,可以为51编程者带来事半功倍的效果,-The document contains a number of popular classics code can be programmed for 51 brought a multiplier effect,
Date : 2008-10-13 Size : 343.25kb User : 王文卓
[Other resource] rc6_avr DL : 0: AVR单片机的优化RC6 加密算法（速度快，其优化思想绝对值得学习）在有128bytes RAM 的AVR单片机上执行 rc6 16/10/8(16 bit/10 rounds/8 bytes keys) * 对多数代码进行了 C 语言优化，对数据相关循环移位，模乘等用ASM优化 * 在4MHz无乘法器的AVR上得到平均 1172 Bytes/s的加解密速度。 * 编译器: AVR-G-AVR optimization RC6 encryption algorithm (faster, optimizing their thinking definitely worth learning) 128bytes of RAM in the AVR on the implementation of production 16/10/8 (16 bit/10 rounds / 8 bytes keys) * for the majority of code optimization of the C language the data related to cycle shift, mode used by other optimization * ASM 4MHz without the multiplier be average AVR 1172 Bytes / s speed encryption and decryption. * Compiler : AVR-G
Date : 2008-10-13 Size : 5.72kb User : 陈谭
[Other resource] 实验5_硬件乘法器操作 DL : 0: ＭＳＰ４３０Ｆ４４９的硬件乘法器操作IAR Practice code-MSP430F449 hardware multiplier operation code IAR Practice
Date : 2008-10-13 Size : 1.03kb User : 顾峰
[Other resource] 乘子法 DL : 0: 优化方法中的解非线性规划问题的一种方法,乘子法-optimization methods of solving nonlinear programming problem in a way Multiplier Method
Date : 2008-10-13 Size : 2.16kb User : 王伟
[Other resource] booth_mul DL : 0: 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols / unsigned multiplication of the number of binary multipliers. The multiplier used to improve the Booth algorithm, simplified some of the plot symbols expansion Wallace tree and used-ahead adder circuit to further enhance the computing speed. The multiplier can be used as embedded CPU cores multiplication modules, the entire design with VHDL.
Date : 2008-10-13 Size : 19.29kb User : 李鹏
[Other resource] Temp DL : 0: 在ｃｍａｋｅ的使用中会遇到很多问题，如果你适当的利用其提供的例子，会收到事半功倍的效果-in cmake use will face a lot of problems, if you use its appropriate for example, will have a multiplier effect
Date : 2008-10-13 Size : 212.91kb User : 韶峰
[Other resource] pipemult DL : 0: 该源码实现了一个8*8位的乘法器，在实现的过程中用到了宏单元-the source to achieve an 8 * 8 Multiplier that in the process modules used Acer
Date : 2008-10-13 Size : 333.87kb User : 倪璠
[Other resource] Booth_Multiplier DL : 0: 布斯乘法器的VHDL程序,下載後直接解壓縮複製貼上到你的EDATOOL就可以.-Booth multiplier VHDL procedures downloaded directly extract copy affixed to the EDATOOL you can.
Date : 2008-10-13 Size : 1.75kb User : 韓堇
[Other resource] VHDL5 DL : 0: 加法器乘法器电路除法器电路设计键盘扫描电路设计显示电路-Adder multiplier circuit divider circuit design keyboard scan circuit design show circuit, etc.
Date : 2008-10-13 Size : 6.45kb User : ngy68
[Other resource] mul6 DL : 1: 用vhdl语言设计CPU中的一部分：乘法器的设计，包括多种乘法器的设计方法！内容为英文-design using VHDL language part of the CPU : multiplier design, Multiplier including multiple design! As for the English
Date : 2008-10-13 Size : 452.73kb User : qindao
[Other resource] wbm DL : 0: 用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.-algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company's paid Multiplier ip core.
Date : 2008-10-13 Size : 2.61kb User : 蒋雯丽
[Other resource] mul4 DL : 0: --- -initial--- - MOVLA 00H IODIR PA IODIR PB IODIR PC MOVAM PA MOVAM BSR MOVAM STATUS MOVAM TMR0 MOVAM TMR1 MOVAM TMR2 -------end initial----- -------------乘法运算------------ 乘数->10H 被乘数->11h 结果(积)->12H 14H 15H 16H 17H(中间运算) --------------------------------- MOVLA 05H 乘数 ---- ---- --- - MOVLA 00H IODI R PA IODIR PB IODIR PC MOVAM PA MOVAM BSR MOVAM STA TUS MOVAM TMR0 MOVAM TMR1 MOVAM TMR2 ------- end initial multiplication ----- ------------- ----------- - multiplier -
Date : 2008-10-13 Size : 1.76kb User : frankyq
[Other resource] add_multi DL : 0: 移位相加硬件乘法器,基于FPGA的VHDL语言编写的,含有全部文件-displacement add hardware multiplier, based on FPGA VHDL prepared, containing all the documents
Date : 2008-10-13 Size : 3.38kb User : 相耀
[Other resource] BoothMultiplier DL : 0: -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn--- Booth Multiplier -- This file contains a ll the entity-architectures for a complete -- k - bit x k-bit Booth multiplier. -- the design mak es use of the new shift operators available in th e VHDL-93 std -- this design passes the Synplify synthesis check -- download from : www.fpga.com.cn
Date : 2008-10-13 Size : 1.79kb User : 罗兰
[Other resource] lpm_mul DL : 0: ８＊８的乘法器verilog源代码,经过编译仿真的，绝对真确，对初学者很有帮助-8 * 8 Multiplier verilog source code, compiled simulation, absolute authenticity, helpful for beginners
Date : 2008-10-13 Size : 27.15kb User : 刘东辉
[Other resource] mult8x8 DL : 0: 一个用VerilogHDL语言编写的8X8的乘法器-a Verilog HDL language used in the preparation of the multiplier 8X8
Date : 2008-10-13 Size : 17.08kb User : 胡东
[Other resource] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE) DL : 0: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
Date : 2008-10-13 Size : 175.34kb User : 李中伟
[Other resource] verilog_multiplier DL : 1: verilog实现16*16位乘法器，带测试文件-verilog achieve 16 * 16 multiplier, with test documents
Date : 2008-10-13 Size : 25.09kb User : zzm

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