Description: using Verilog cpld written by the various sub-frequency procedures in the hope that we stand corrected, thank you!
- [fen] - Verilog, 4,5 dividers, five dividers rat
- [fpga1394] - This is a control chip cpld 1394 Verilog
- [sdram4m16_L2_42] - FPGA SDRAM with the operation of the spe
- [div_3] - Verilog three dividers and documents con
- [yyin] - This a voice procedures, through a VHDL
- [APopupMenActX] - a popup menu ActiveX control, it enables
- [Verilog_FPGA_fp] - using Verilog FPGA-based Universal Frequ
- [11-1divide5_new_method] - This is a five-frequency circuit design,
- [cpld] - a handy integer frequency divider circui
- [UART] - Using FPGA to achieve the RS232 asynchro
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