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Title: hdlc_decode Download
 Description: The HDLC decoder based on Verilog. Which are extracted using digital phase-locked loop clock
 Downloaders recently: [More information of uploader 09121958]
 To Search: hdlc verilog
  • [frame_decode_and_encode] - Verilog prepared with a series of frames
  • [hdlc] - HDLC protocol controller, implemented wi
  • [hdlc_encode] - HDLC-based Verilog decoder. Output of an
  • [dpll] - Verilog-based digital PLL. Consists of t
  • [open_cores_VGAcore] - Written by foreigners wishbone bus proto
  • [HDLC] - written in verilog HDL HDLC protocol IP
File list (Check if you may need any files):
hdlc_decode\db\hdlc_decode.asm.qmsg
...........\..\hdlc_decode.cbx.xml
...........\..\hdlc_decode.cmp.bpm
...........\..\hdlc_decode.cmp.cdb
...........\..\hdlc_decode.cmp.ecobp
...........\..\hdlc_decode.cmp.hdb
...........\..\hdlc_decode.cmp.logdb
...........\..\hdlc_decode.cmp.rdb
...........\..\hdlc_decode.cmp.tdb
...........\..\hdlc_decode.cmp0.ddb
...........\..\hdlc_decode.db_info
...........\..\hdlc_decode.eco.cdb
...........\..\hdlc_decode.eda.qmsg
...........\..\hdlc_decode.fit.qmsg
...........\..\hdlc_decode.hier_info
...........\..\hdlc_decode.hif
...........\..\hdlc_decode.map.bpm
...........\..\hdlc_decode.map.cdb
...........\..\hdlc_decode.map.ecobp
...........\..\hdlc_decode.map.hdb
...........\..\hdlc_decode.map.logdb
...........\..\hdlc_decode.map.qmsg
...........\..\hdlc_decode.map_bb.cdb
...........\..\hdlc_decode.map_bb.hdb
...........\..\hdlc_decode.map_bb.hdbx
...........\..\hdlc_decode.map_bb.logdb
...........\..\hdlc_decode.pre_map.cdb
...........\..\hdlc_decode.pre_map.hdb
...........\..\hdlc_decode.psp
...........\..\hdlc_decode.root_partition.cmp.atm
...........\..\hdlc_decode.root_partition.cmp.dfp
...........\..\hdlc_decode.root_partition.cmp.hdbx
...........\..\hdlc_decode.root_partition.cmp.logdb
...........\..\hdlc_decode.root_partition.cmp.rcf
...........\..\hdlc_decode.root_partition.map.atm
...........\..\hdlc_decode.root_partition.map.hdbx
...........\..\hdlc_decode.root_partition.map.info
...........\..\hdlc_decode.rtlv.hdb
...........\..\hdlc_decode.rtlv_sg.cdb
...........\..\hdlc_decode.rtlv_sg_swap.cdb
...........\..\hdlc_decode.sgdiff.cdb
...........\..\hdlc_decode.sgdiff.hdb
...........\..\hdlc_decode.signalprobe.cdb
...........\..\hdlc_decode.sld_design_entry.sci
...........\..\hdlc_decode.sld_design_entry_dsc.sci
...........\..\hdlc_decode.smp_dump.txt
...........\..\hdlc_decode.syn_hier_info
...........\..\hdlc_decode.tan.qmsg
...........\..\hdlc_decode.tis_db_list.ddb
...........\..\prev_cmp_hdlc_decode.asm.qmsg
...........\..\prev_cmp_hdlc_decode.fit.qmsg
...........\..\prev_cmp_hdlc_decode.map.qmsg
...........\..\prev_cmp_hdlc_decode.qmsg
...........\..\prev_cmp_hdlc_decode.tan.qmsg
...........\dco.v
...........\dlf.v
...........\dpd.v
...........\dpll.v
...........\hdlc_decode.asm.rpt
...........\hdlc_decode.done
...........\hdlc_decode.eda.rpt
...........\hdlc_decode.fit.rpt
...........\hdlc_decode.fit.smsg
...........\hdlc_decode.fit.summary
...........\hdlc_decode.flow.rpt
...........\hdlc_decode.map.rpt
...........\hdlc_decode.map.smsg
...........\hdlc_decode.map.summary
...........\hdlc_decode.pin
...........\hdlc_decode.pof
...........\hdlc_decode.qpf
...........\hdlc_decode.qsf
...........\hdlc_decode.qws
...........\hdlc_decode.sof
...........\hdlc_decode.tan.rpt
...........\hdlc_decode.tan.summary
...........\hdlc_decode.v
...........\simulation\modelsim\altera_mf.v
...........\..........\........\cyclone_atoms.v
...........\..........\........\hdcl_decode.cr.mti
...........\..........\........\hdcl_decode.mpf
...........\..........\........\hdlc_decode.sft
...........\..........\........\hdlc_decode.vo
...........\..........\........\hdlc_decode_modelsim.xrf
...........\..........\........\hdlc_decode_v.sdo
...........\..........\........\top.v
...........\..........\........\top.v.bak
...........\..........\........\vsim.wlf
...........\..........\........\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
...........\..........\........\....\..........................................\_primary.dat
...........\..........\........\....\..........................................\_primary.vhd
...........\..........\........\....\.c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e\verilog.asm
...........\..........\........\....\................................\_primary.dat
...........\..........\........\....\................................\_primary.vhd
...........\..........\........\....\.m@f_pll_reg\verilog.asm
...........\..........\........\....\............\_primary.dat
...........\..........\........\....\............\_primary.vhd
...........\..........\........\....

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