Description: Use verilog to write a variable width of the output data FIFO, input data for the 32-bit, output data can be configured as 4-1 arbitrary bit. There are design files and testbench
- [FIFO_v] - FIFO verilog achieve, enclosing testbenc
- [asynchoronization_FIFO_design] - Verilog HDL language programming, Async
- [FPGA_FIFO] - Prepared by the use of Verilog synchrono
- [fifo] - A First in first out buffer in Verilog
- [fifo] - Asynchronous fifo, to prepare to use Ver
- [asynfifo] - Asynchronous fifo, to prepare to use Ver
File list (Check if you may need any files):
fifo_32_4321
............\fifo_32_4321.v
............\tb_ff_32_4321.v
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