Description: Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
- [Verilog-golden] - VHDL version, I spent nine cattle to fin
- [FIFO_v] - FIFO verilog achieve, enclosing testbenc
- [s_fifo] - Verilog language describes a synchronous
- [FIFO] - Verilog development FIFO, after verifica
- [WritingTestbenches] - Testbench prepared super good tutorials,
- [FIFO] - Asynchronous FIFO verilog realize realiz
- [FIFO] - Verilog using Asynchronous FIFO, the cod
- [68013_SlaveFIFO] - cy7c68013 slave fifo mode code ,written
- [fifo_32_4321] - Use verilog to write a variable width of
- [FIFO_GRAY] - FIFO - binary to gray code pointer conve
File list (Check if you may need any files):
0804214-段振华-fifo程序
.......................\fifo
.......................\....\fifo.cr.mti
.......................\....\fifo.mpf
.......................\....\fifo.v
.......................\....\fifo.v.bak
.......................\....\fifotb.v
.......................\....\fifotb.v.bak
.......................\....\transcript
.......................\....\vish_stacktrace.vstf
.......................\....\vsim.wlf
.......................\....\work
.......................\....\....\fifo
.......................\....\....\....\verilog.asm
.......................\....\....\....\_primary.dat
.......................\....\....\....\_primary.vhd
.......................\....\....\gray
.......................\....\....\....\verilog.asm
.......................\....\....\....\_primary.dat
.......................\....\....\....\_primary.vhd
.......................\....\....\testfifo
.......................\....\....\........\verilog.asm
.......................\....\....\........\_primary.dat
.......................\....\....\........\_primary.vhd
.......................\....\....\_info
.......................\fifo程序说明.doc
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