Description: Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH settings, FIFO_WRITE_CLOCK rising edge to the FIFO write data, FIFO_READ_CLOCK rising edge of read data. This procedure on the upper FIFO operation simple and practical.
- [simple_fifo] - verilog HDL original code a simple synch
- [ram] - primitive code using VHDL prepared RAM,
- [s_fifo] - Verilog language describes a synchronous
- [fifo] - A synchronous FIFO, including the testbe
- [uart8] - Libero provided the use of asynchronous
- [fifo] - synchronous fifo code
- [fifo] - Synchronizing FIFO creates a 256x8 synch
- [fifo] - this the syn-fifo,including testbench
- [fifo_32_4321] - Use verilog to write a variable width of
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FIFO.v
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