Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: fifo Download
 Description: Synchronizing FIFO creates a 256x8 synchronous FIFO, and initializes FIFO through the serial port, and FIFO data inside the FPGA is sent through the window to pc-fifo
 Downloaders recently: [More information of uploader jom2729]
 To Search: FPGA fifo fifo FIFo VHDL vhdl fifo fifo adpcm
File list (Check if you may need any files): 
ctrl_FIFO.v
FIFO_top.v
rec.v
send.v

CodeBus www.codebus.net