Description: verilog written communication and computer uart, I had the experiment, everything is very good, very good work
- [uart-verilog-vhdl] - with vhdl and verilog prepared by the se
- [UART] - UART serial procedures, verilog statemen
- [UART_send] - Verilog HDL send serial procedures, ACTE
- [uart(Verilog)] - RS232 verilog source code, if necessary
- [trafficlight_verilog] - Verilog Language realize traffic lights,
- [mini-uart] - Verilog implementation mini-uart, code F
- [trafficlights] - Mainly to achieve complete control of ro
- [rs232] - Full RS232 Verilog source code, support
- [UART] - I have written of the FPGA asynchronous
- [asic_study] - ASCI is compressed package learning mate
File list (Check if you may need any files):
新建文件夹
..........\clock.bsf
..........\clock.v
..........\dcfifo1.bsf
..........\dcfifo1.v
..........\dcfifo1_bb.v
..........\rxdpart.bsf
..........\rxdpart.v
..........\sync.bsf
..........\sync.v
..........\txdpart.bsf
..........\txdpart.v
..........\uuu.bdf
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