fifo Using dual-port ram realize asynchronous , th - CodeBus

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Title: fifo

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
1.08kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
shilifeng

Description: Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.

Downloaders recently: [More information of uploader shilifeng]

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