alu 4bit ALU (arithmetic logic unit) design is giv

Title: alu

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
1.56kb
Update:
2008-10-13
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Uploaded by:
chysherry

Description: 4bit ALU (arithmetic logic unit) design is given in the design of alu input and output structure and the corresponding median. C0 which is a binary input of, A and B are four data entry, S0, S1, M, respectively, as a function of choice of the input signal Cout of a binary output, F is 4 for computing the results of output.

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