clk_div Verilog realize multi-clock, can be applie - CodeBus

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Title: clk_div

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
1.36kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
kaimen1982

Description: Verilog realize multi-clock, can be applied to assembly line. Input CLK, the output CLK1, CLK2, CLK3

Downloaders recently: [More information of uploader kaimen1982]

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