VHDL-FPGA-Verilog List Page 999

VHDL-FPGA-Verilog list

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lasted Downloaded：0: Contest scoring system. Can calculate the mandatory questions and grab answer scores, and its ranking.
Date : 2025-08-11 Size : 1kb User : 蒋维
IrDA_tx Downloaded：0: VerilogHDL IRDA TX RTL source code
Date : 2025-08-11 Size : 1kb User : zengshengjin
IrDA_rx Downloaded：0: VerilogHDL IRDA RX RTL Source code
Date : 2025-08-11 Size : 1kb User : zengshengjin
clk_generator Downloaded：0: clock divider，PWM generator RTL Source Code
Date : 2025-08-11 Size : 1kb User : zengshengjin
uart_rx Downloaded：0: VerilogHDL UART RX RTL SOURCE CODE
Date : 2025-08-11 Size : 1kb User : zengshengjin
uart_tx Downloaded：0: Verilog HDL UART TX RTL SOURCE CODE
Date : 2025-08-11 Size : 1kb User : zengshengjin
siweijishu Downloaded：0: verilog four decimal counter
Date : 2025-08-11 Size : 292kb User : water
shixukongzhi Downloaded：0: verilog timing frequency timing control module used to do.
Date : 2025-08-11 Size : 266kb User : water
chengfaleijia Downloaded：0: verilog multiplier-accumulator including the project and the simulation waveform
Date : 2025-08-11 Size : 580kb User : water
LPM_RAM Downloaded：0: verilog parameter can be set to call the module RAM
Date : 2025-08-11 Size : 143kb User : water
pinlvji Downloaded：0: verilog simple frequency meter settings, including the entire project
Date : 2025-08-11 Size : 354kb User : water
shizhong_xianshi Downloaded：0: Using Altera FPGA-based digital clock, using the key display, with timing function when adjusting
Date : 2025-08-11 Size : 685kb User :

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