VHDL-FPGA-Verilog List Page 996

VHDL-FPGA-Verilog list

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I2C_SPI_UART__CME Downloaded：0: Beijing micro Accord FPGA interface routines, several common interface, for 51 cores
Date : 2025-08-11 Size : 222kb User : yy
lqz2 Downloaded：0: 4 BCD code to binary code converter
Date : 2025-08-11 Size : 6.56mb User : 李求知
lqz3 Downloaded：0: This procedure is reversible with synchronous set (plus one or minus one) 5 binary counter
Date : 2025-08-11 Size : 523kb User : 李求知
lqz4 Downloaded：0: This program is a bidirectional shift with a set string into/out of 6-bit shift register and
Date : 2025-08-11 Size : 517kb User : 李求知
lqz6 Downloaded：0: This procedure can be achieved using graphical input, to achieve a 4-bit binary full adder.
Date : 2025-08-11 Size : 568kb User : 李求知
EP2C8-2010_FPGA Downloaded：0: # Copyright (C) 1991-2009 Altera Corporation # Your use of Altera Corporation s design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the f
Date : 2025-08-11 Size : 3.67mb User : wqc
DE2_Top Downloaded：0: altera DE2 development board important application interfaces, including VGA, Ethernet communications, audio and video decoding, the subsequent development of routines which can be used directly when the port
Date : 2025-08-11 Size : 37kb User : 叶志远
DE2_NIOS_HOST_MOUSE_VGA Downloaded：0: VGA monitor and mouse combination, demonstrates how to use the mouse to control the image on the VGA monitor
Date : 2025-08-11 Size : 2.17mb User : 叶志远
DE2_SD_Card_Audio Downloaded：0: SD card and audio decoding apparatus combined routines, using the environment as altera DE2 development board can be directly compiled to use
Date : 2025-08-11 Size : 2.07mb User : 叶志远
DE2_USB_API Downloaded：0: Based on altera DE2 development board USB application process can be achieved with the control of the FPGA, including the input data to the SRAM, the replacement of VGA display pictures, etc.
Date : 2025-08-11 Size : 1.93mb User : 叶志远
DE2_NET Downloaded：0: altera DE2 development board and network communication routines, using nios ii system
Date : 2025-08-11 Size : 2.34mb User : 叶志远
div_clk Downloaded：0: Achieve any clock divider, simple, open modelsim-change directroy-do sim. Do to
Date : 2025-08-11 Size : 40kb User :

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