VHDL-FPGA-Verilog List Page 998

VHDL-FPGA-Verilog list

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div_freq Downloaded：0: Altera' s FPGA development using a frequency synthesizer, the realization of the input frequency halved and quartered, eight equal portions and so on.
Date : 2025-08-11 Size : 468kb User :
eetop.cn_quartus_design Downloaded：0: The basic syntax for entry-learning verilog video to explain
Date : 2025-08-11 Size : 8.24mb User : moke
eetop.cn_quartus_pgm Downloaded：0: verilog basic syntax of introductory video tutorials flash
Date : 2025-08-11 Size : 3.85mb User : moke
baker-code-generator Downloaded：0: baker code generator
Date : 2025-08-11 Size : 287kb User : sddxzq
_50MHz--1Hz Downloaded：0: Divider circuit can be divided into the DE2 board 1Hz output on 50MHz, absolutely feasible, with a simulation program!
Date : 2025-08-11 Size : 370kb User : wancaihong
jiancedianlu Downloaded：0: Function is to detect the serial input data Sin the 4-bit binary sequence 0101 (from left to right input), when the sequence is detected, the output Out = 1 the sequence is not detected, the output Out = 0.
Date : 2025-08-11 Size : 301kb User : wancaihong
4weiquanjiaqi Downloaded：0: 4 full adder by the three modules. First, the basic gate-level component instance references xor, and define the underlying half-adder module halfadder, then cite two examples of half-adder module halfadder and a base or
Date : 2025-08-11 Size : 393kb User : wancaihong
shuzihongdianlu Downloaded：0: Digital clock circuit implementation, a 24-hour timer, adjustable time!
Date : 2025-08-11 Size : 367kb User : wancaihong
qicehweideng Downloaded：0: Control circuit design taillights, normal driving, six taillights Quanmie, brake, tail lights flashing at a certain frequency, turn left, turn left flashing lights, turn right, the right lights flash alternately.
Date : 2025-08-11 Size : 1kb User : wancaihong
PHA Downloaded：0: Verilog prepared by the two-way signal phase measurements related content, calculate the phase difference between two signals, and the current frequency
Date : 2025-08-11 Size : 1kb User : 常艺
Latch Downloaded：0: Latch on behalf of the FPGA using verilog HDL
Date : 2025-08-11 Size : 2kb User : sheng
FREQMODN Downloaded：0: Described in verilog verilog code divider circuit
Date : 2025-08-11 Size : 2kb User : sheng

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