Altera' s FPGA development using a frequency synthesizer, the realization of the input frequency halved and quartered, eight equal portions and so on.

div_freq\cymometer.bsf
........\cymometer.vhd
........\db\divfreq_top.asm.qmsg
........\..\divfreq_top.asm_labs.ddb
........\..\divfreq_top.cbx.xml
........\..\divfreq_top.cmp.cdb
........\..\divfreq_top.cmp.hdb
........\..\divfreq_top.cmp.kpt
........\..\divfreq_top.cmp.logdb
........\..\divfreq_top.cmp.rdb
........\..\divfreq_top.cmp.tdb
........\..\divfreq_top.cmp0.ddb
........\..\divfreq_top.cmp2.ddb
........\..\divfreq_top.dbp
........\..\divfreq_top.db_info
........\..\divfreq_top.eco.cdb
........\..\divfreq_top.fit.qmsg
........\..\divfreq_top.hier_info
........\..\divfreq_top.hif
........\..\divfreq_top.map.cdb
........\..\divfreq_top.map.hdb
........\..\divfreq_top.map.logdb
........\..\divfreq_top.map.qmsg
........\..\divfreq_top.pre_map.cdb
........\..\divfreq_top.pre_map.hdb
........\..\divfreq_top.psp
........\..\divfreq_top.rtlv.hdb
........\..\divfreq_top.rtlv_sg.cdb
........\..\divfreq_top.rtlv_sg_swap.cdb
........\..\divfreq_top.sgdiff.cdb
........\..\divfreq_top.sgdiff.hdb
........\..\divfreq_top.signalprobe.cdb
........\..\divfreq_top.sld_design_entry.sci
........\..\divfreq_top.sld_design_entry_dsc.sci
........\..\divfreq_top.syn_hier_info
........\..\divfreq_top.tan.qmsg
........\divfreq_top.asm.rpt
........\divfreq_top.bdf
........\divfreq_top.cdf
........\divfreq_top.done
........\divfreq_top.dpf
........\divfreq_top.fit.rpt
........\divfreq_top.fit.smsg
........\divfreq_top.fit.summary
........\divfreq_top.flow.rpt
........\divfreq_top.map.rpt
........\divfreq_top.map.summary
........\divfreq_top.pin
........\divfreq_top.pof
........\divfreq_top.qpf
........\divfreq_top.qsf
........\divfreq_top.qws
........\divfreq_top.sof
........\divfreq_top.tan.rpt
........\divfreq_top.tan.summary
........\div_half.bsf
........\div_half.vhd
........\db
div_freq

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