Using Altera FPGA-based digital clock, using the key display, with timing function when adjusting

shizhong_xianshi\clock.asm.rpt
................\clock.cdf
................\clock.done
................\clock.dpf
................\clock.fit.rpt
................\clock.fit.smsg
................\clock.fit.summary
................\clock.flow.rpt
................\clock.map.rpt
................\clock.map.summary
................\clock.pin
................\clock.pof
................\clock.qpf
................\clock.qsf
................\clock.qws
................\clock.sim.rpt
................\clock.sof
................\clock.tan.rpt
................\clock.tan.summary
................\clock.vhd
................\clock.vwf
................\db\add_sub_lkc.tdf
................\..\add_sub_mkc.tdf
................\..\alt_u_div_ive.tdf
................\..\alt_u_div_kve.tdf
................\..\alt_u_div_lve.tdf
................\..\alt_u_div_ove.tdf
................\..\clock.asm.qmsg
................\..\clock.asm_labs.ddb
................\..\clock.cbx.xml
................\..\clock.cmp.cdb
................\..\clock.cmp.hdb
................\..\clock.cmp.kpt
................\..\clock.cmp.logdb
................\..\clock.cmp.rdb
................\..\clock.cmp.tdb
................\..\clock.cmp0.ddb
................\..\clock.cmp2.ddb
................\..\clock.dbp
................\..\clock.db_info
................\..\clock.eco.cdb
................\..\clock.eds_overflow
................\..\clock.fit.qmsg
................\..\clock.fnsim.hdb
................\..\clock.fnsim.qmsg
................\..\clock.hier_info
................\..\clock.hif
................\..\clock.map.cdb
................\..\clock.map.hdb
................\..\clock.map.logdb
................\..\clock.map.qmsg
................\..\clock.pre_map.cdb
................\..\clock.pre_map.hdb
................\..\clock.psp
................\..\clock.rtlv.hdb
................\..\clock.rtlv_sg.cdb
................\..\clock.rtlv_sg_swap.cdb
................\..\clock.sgdiff.cdb
................\..\clock.sgdiff.hdb
................\..\clock.signalprobe.cdb
................\..\clock.sim.hdb
................\..\clock.sim.qmsg
................\..\clock.sim.rdb
................\..\clock.sim.vwf
................\..\clock.sld_design_entry.sci
................\..\clock.sld_design_entry_dsc.sci
................\..\clock.syn_hier_info
................\..\clock.tan.qmsg
................\..\lpm_divide_25m.tdf
................\..\lpm_divide_45m.tdf
................\..\lpm_divide_ucm.tdf
................\..\lpm_divide_vcm.tdf
................\..\mux_0kc.tdf
................\..\mux_5kc.tdf
................\..\mux_llc.tdf
................\..\sign_div_unsign_8kh.tdf
................\..\sign_div_unsign_9kh.tdf
................\..\sign_div_unsign_akh.tdf
................\..\sign_div_unsign_bkh.tdf
................\..\wed.zsf
................\output_file.map
................\output_file.pof
................\db
shizhong_xianshi

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