VHDL-FPGA-Verilog List Page 951

VHDL-FPGA-Verilog list

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sw_debounce Downloaded：0: Key debounce
Date : 2025-08-04 Size : 1kb User : 卢磊
flash-led Downloaded：0: Language verilog fpga hardware utilization under a simple light water experiment, three lights to achieve pipelined to achieve a flashing operation, a very good introductory reference to the classic examples
Date : 2025-08-04 Size : 118kb User : havi
FPGA(QII) Downloaded：0: FPGA AND alter SIN SAN JIAO BO JUCHIBO FANG BO
Date : 2025-08-04 Size : 4mb User : 小华
MFSK-VHDL Downloaded：0: Based on the VHDL hardware description language, complete baseband signal MFSK modulation
Date : 2025-08-04 Size : 62kb User : MOHAMAD
motor-VHDL Downloaded：0: Stepper motor positioning control system procedures and VHDL simulation
Date : 2025-08-04 Size : 5kb User : MOHAMAD
FSK-VHDL Downloaded：0: VHDL hardware description language based on FSK modulation baseband signal
Date : 2025-08-04 Size : 51kb User : MOHAMAD
wtut_ver.ZIP Downloaded：0: Stopwatch program, complete verilog project file, complete engineering design process, including the timing constraints, ip nuclear embedding, as well as the use of DCM module
Date : 2025-08-04 Size : 455kb User : luojian
Verilog--Tutorial Downloaded：0: Verilog language tutorial, including the structure of the language, the command character, identifiers etc. the use of grammar, and a variety of entry test routines.
Date : 2025-08-04 Size : 4.47mb User : 孙开环
CJQ-V1.0-fpga Downloaded：0: it is good
Date : 2025-08-04 Size : 2.24mb User : gh
UART_Trans Downloaded：0: An FPGA is working properly used to test the procedure, the main function is to transmit serial data
Date : 2025-08-04 Size : 1.72mb User : 许闯
dpll2 Downloaded：0: Vdhl DPLL implementation, the phase detector, a counter, a voltage controlled oscillator, and a frequency divider
Date : 2025-08-04 Size : 1kb User : 朱小波
Altera_FPGA_CPLD Downloaded：0: Altera_FPGA_CPLD study notes privilege perfect finishing
Date : 2025-08-04 Size : 23kb User : 灵湖仙梦

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