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VHDL-FPGA-Verilog list
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FPGA-based I2C communication code, tested on the development board, welcome
Date : 2026-01-14 Size : 724kb User : 岳振

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VGA display
Date : 2026-01-14 Size : 4kb User : 方颀

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Based on the FPGA using verilog language, change the program can produce different coefficients and different frequency modulated AM wave, long press the button to switch the modulation of 25 , 50 , 75 and short press bu
Date : 2026-01-14 Size : 981kb User : 尹佳佳

VHDL-based digital clock design, you can adjust the time, and you can set four alarm time, and in a lot of VHDL basic procedures, useful for beginners
Date : 2026-01-14 Size : 10kb User :

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Completion of the master clock frequency divider quarter, we want to help.
Date : 2026-01-14 Size : 38kb User : 王世豪

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Iic main communications protocol for doing simple rules, through verilog language settings.
Date : 2026-01-14 Size : 3kb User : 王世豪

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Use verilog to decode for ps2, ps2 make everyone a better understanding.
Date : 2026-01-14 Size : 1kb User : 王世豪

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. Typical RS232 signal level swing between positive and negative, when data is transmitted, the transmitter side driver outputs a positive level in+5 ~+15V, negative level at-5 ~-15V level. Typical operating the receiver
Date : 2026-01-14 Size : 1kb User : 王世豪

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The project design requires a VGA monitor to display a blue background, the central display a green border and a pink rectangle
Date : 2026-01-14 Size : 1kb User : 王世豪

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The experimental realization of a two digital tube while loop increments from 0 to F function.
Date : 2026-01-14 Size : 1kb User : 王世豪

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In this experiment is to use sequential logic design method to design a 16-bit multiplier
Date : 2026-01-14 Size : 1kb User : 王世豪

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The experimental realization of the SRAM to traverse each address read and write operations, and then compared before and after the data is read Correct, and finally through an LED for indicating the bright lights
Date : 2026-01-14 Size : 1kb User : 王世豪
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