VHDL-FPGA-Verilog List Page 947

VHDL-FPGA-Verilog list

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divider13 Downloaded：0: This a 13 frequency divider which can transfer the input clock signal into a 1/13 clock signal.
Date : 2026-01-14 Size : 2kb User : 陈楠
divider8 Downloaded：0: This a 8 frequency divider which can transfer the input clock signal into 1/8 clock
Date : 2026-01-14 Size : 2kb User : 陈楠
divider256 Downloaded：0: This a 2 to 256 frequency divider which can transfer the input clock signal into 1/2 to 1/256 clock
Date : 2026-01-14 Size : 3kb User : 陈楠
ramIPcore Downloaded：0: Based on the ram quartusII calls itself blockram created using FPGA ram' s ip core
Date : 2026-01-14 Size : 728kb User : yuyeluo
Virtex5user-guide Downloaded：0: VIRTEX development must the Chinese documents, very suitable for beginners to learn and learn from Comrade xilinx primitives
Date : 2026-01-14 Size : 4.46mb User : wang
xilinx-forHDLDesigns Downloaded：0: VIRTEX primitives library file Chinese documents, very suitable for beginners to learn and learn from Comrade xilinx primitives
Date : 2026-01-14 Size : 1.24mb User : wang
xilinx-forSchematicDesigns Downloaded：0: VIRTEX schematic primitives library file Chinese documents, very suitable for beginners to learn and learn from Comrade xilinx primitives
Date : 2026-01-14 Size : 2.37mb User : wang
Xilinx-language Downloaded：0: Xilinx glossary of terms, suitable for beginners to learn research, can also be used as a research and development
Date : 2026-01-14 Size : 267kb User : wang
FPGA_to_STM32 Downloaded：0: FPGA and a program to communicate stm32 serial communication
Date : 2026-01-14 Size : 201kb User : 郭凌云
calc Downloaded：0: A simple calculator verilog design, keyboard input, digital display, Modified with OR operator
Date : 2026-01-14 Size : 2.9mb User : suber
DDS_TLC5620 Downloaded：0: dds tlc5620 verilog
Date : 2026-01-14 Size : 3.66mb User : 董辉辉
FPGA_CPU Downloaded：0: FPGA VERILOG CPU
Date : 2026-01-14 Size : 458kb User : 董辉辉

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