VHDL-FPGA-Verilog List Page 883

VHDL-FPGA-Verilog list

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edge Downloaded：0: fpga edge interrupt detection procedures, the procedures can be used nios II simulation.
Date : 2025-07-28 Size : 11.15mb User : 赵莉
rtc Downloaded：0: NIOS II development for the next RTC real time clock, have more knowledge of difficulty: . 1 PIO depth application 2 Application C language function pointers . 3 DS1302 driver to prepare 4 modular program in C language n
Date : 2025-07-28 Size : 11.27mb User : 赵莉
quartus_works_first Downloaded：1: Based verilog language, FPGA program implementation can pause the timer with digital display function, time range from 0 to 99 seconds, precision 0.01 seconds, measured by the EP1C3T100C8 pro
Date : 2025-07-28 Size : 489kb User : FT_Young
int Downloaded：0: To carry out the experiment through the key level interrupt interrupted, the program can use DEBUG mode for online debugging
Date : 2025-07-28 Size : 10.6mb User : 赵莉
quartus_works_second Downloaded：0: Based verilog language, FPGA procedures to achieve frequency meter with digital display, switching frequency 48M, precision 1Hz, range 1Hz ~ 9999Hz, frequency and ultra-frequency tips lacks accuracy and range can vary wi
Date : 2025-07-28 Size : 4mb User : FT_Young
iic Downloaded：0: By using a single-chip FPGA IIC bus read and write on 24LC04 experiments. Write 512btye data, the first 256 digits from 0 to 255, after 256 data 1. Then, read 512byte data and print out. Finally, comparative data is the
Date : 2025-07-28 Size : 11.27mb User : 赵莉
flash Downloaded：0: Using a FPGA chip FLASH experiment conducted under the NIOS II Experiment: The number 100 is written to FLASH, and then read and print them out.
Date : 2025-07-28 Size : 11.16mb User : 赵莉
QUARTUS_WORK_FORTH Downloaded：0: Based verilog language, FPGA program FPGA serial digital transmission of computer and hardware devices to EP1C3T100C8, usb to RS232 chip FT232BM,
Date : 2025-07-28 Size : 584kb User : FT_Young
jpeg_encoder Downloaded：0: JPEG Encoder IP Core,The core is written in Verilog and is designed to be portable to any target device. This core does not perform subsampling- the resulting JPEG image will have 4:4:4 subsampling
Date : 2025-07-28 Size : 175kb User : jwchen
vhd4 Downloaded：0: Just like
Date : 2025-07-28 Size : 175kb User : chlong
third Downloaded：0: Just like
Date : 2025-07-28 Size : 1.32mb User : chlong
tugas-1 Downloaded：0: Coding VHDL Substractor adder
Date : 2025-07-28 Size : 20kb User : akbar

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