VHDL-FPGA-Verilog List Page 878

VHDL-FPGA-Verilog list

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lcd1602_test Downloaded：0: Experimental basis 07-1602 English characters display experiment-FPGA source code
Date : 2025-07-28 Size : 224kb User : 刘西
buzz_test Downloaded：0: verilog buzzer experiments, for FPGA development board.
Date : 2025-07-28 Size : 91kb User : 刘西
sw_seg_test Downloaded：0: DIP switch input digital display experiment for FPGA development board
Date : 2025-07-28 Size : 116kb User : 刘西
sw_led_test Downloaded：0: DIP switch input LED display experiment for FPGA development board
Date : 2025-07-28 Size : 72kb User : 刘西
bakema Downloaded：0: Bake Ma produced by counting to determine the output of the generator has a reset function
Date : 2025-07-28 Size : 1kb User : lone
RX_TX_FIFO Downloaded：0: Complete serial transceiver module during the restructuring process the data as ne
Date : 2025-07-28 Size : 291kb User : 孟博
Example18 Downloaded：0: voting for seven people，7 people can vote applet
Date : 2025-07-28 Size : 165kb User : 卢进
MY_CAMARA_3_18_FIFO Downloaded：0: the IP core of fpga,can be used in embedded device
Date : 2025-07-28 Size : 26.53mb User : 刘普明
Example1 Downloaded：0: A simple VHDL taxi meter is a small program, mileage is a base price of less than 1Km over another billing
Date : 2025-07-28 Size : 238kb User : 卢进
Example23 Downloaded：0: Design a multi-function digital stopwatch VHDL applet, generate 100Hz clock divider counter
Date : 2025-07-28 Size : 278kb User : 卢进
Example22 Downloaded：0: Based on a small program designed multifunction digital clock divider to generate 1Hz clock counter and running
Date : 2025-07-28 Size : 278kb User : 卢进
Example25 Downloaded：0: VHDL-based design a digital lock small program, which joined the digital display and alarm system
Date : 2025-07-28 Size : 348kb User : 卢进

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