VHDL-FPGA-Verilog List Page 874

VHDL-FPGA-Verilog list

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windows-script Downloaded：0: In the window platform, using classic example TCL script to compile the fpga. Specific wording, see the project ise_flow.bat file. If the workstation to handle more blocks
Date : 2026-01-12 Size : 15kb User : 成功
Zed_vga_hdmi_720p Downloaded：0: Hdmi display board zedboard on using development tools ise, familiar ideo timing and recommend it to everyone
Date : 2026-01-12 Size : 40kb User : 成功
OLED_on_ZedBoard-master Downloaded：0: Control board zedboard on OLED development, the use of development tools ise, familiar OLED works, recommend it to everyone
Date : 2026-01-12 Size : 77kb User : 成功
Getting-Started-with-HW Downloaded：0: Using zedboard, zynq etc. on matlab platform for hardware co-simulation, the article describes the Getting Started with HW, build and debug mode environment.
Date : 2026-01-12 Size : 2.78mb User : 成功
mbq_ResetUSB Downloaded：0: USB controller reset
Date : 2026-01-12 Size : 3kb User : Steven
VHDL-8-wei-quan-jia-qi Downloaded：0: Schematic entry method 8-bit full adder, and a source code file containing the vhd file word description, pin configuration has been completed, the chip is EPIK30TCI443
Date : 2026-01-12 Size : 283kb User :
yi-wei-er-jin-zhi-quan-jia-qi Downloaded：0: A binary full source code and detailed documentation WORD, maxplus software running, pin has been configured, EP1K30TC144-3
Date : 2026-01-12 Size : 130kb User : 邱海涛
shu-kong-fen-pin-qi Downloaded：0: NC divider source code and detailed documentation WORD, maxplus software running, pin has been configured, the chip is EP1K30TC144-3
Date : 2026-01-12 Size : 164kb User : 邱海涛
jia-fa-ji-shu-qi Downloaded：0: Asynchronous and synchronous cleared with the addition of the counter enable source code, run the software with maxplus Pin has been configured, the chip is EP1K30TC144-3
Date : 2026-01-12 Size : 37kb User : 邱海涛
XU-LIE-JIAN-CE-QI Downloaded：0: State of mind achieved with a sequence detector source code, run the software with maxplus Pin has been configured, the chip is EP1K30TC144-3
Date : 2026-01-12 Size : 41kb User : 邱海涛
cai-yang-dian-lu-shi-xian-ADC0809 Downloaded：0: State machine to achieve ADC0809 sampling control circuit of the source code, run the software with maxplus Pin has been configured, the chip is EP1K30TC144-3
Date : 2026-01-12 Size : 41kb User : 邱海涛
Example9 Downloaded：0: An FPGA-based four full adder applet, enter two binary numbers and calculations.
Date : 2026-01-12 Size : 138kb User : 卢进

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