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RX_TX_FIFO

  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-01-07
  • Size : 291kb
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  • Author :孟***
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Introduction - If you have any usage issues, please Google them yourself
Complete serial transceiver module during the restructuring process the data as ne
Packet file list
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RX_TX_FIFO\FIFO.bsf
..........\RX_TX_FIFO.asm.rpt
..........\RX_TX_FIFO.cdf
..........\RX_TX_FIFO.done
..........\RX_TX_FIFO.eda.rpt
..........\RX_TX_FIFO.fit.rpt
..........\RX_TX_FIFO.fit.smsg
..........\RX_TX_FIFO.fit.summary
..........\RX_TX_FIFO.flow.rpt
..........\RX_TX_FIFO.jdi
..........\RX_TX_FIFO.map.rpt
..........\RX_TX_FIFO.map.summary
..........\RX_TX_FIFO.pin
..........\RX_TX_FIFO.qpf
..........\RX_TX_FIFO.qsf
..........\RX_TX_FIFO.qws
..........\RX_TX_FIFO.sof
..........\RX_TX_FIFO.sta.rpt
..........\RX_TX_FIFO.sta.summary
..........\RX_TX_FIFO_assignment_defaults.qdf
..........\source\detect_module.v
..........\......\detect_module.v.bak
..........\......\FIFO.bsf
..........\......\FIFO.qip
..........\......\FIFO.v
..........\......\FIFO_bb.v
..........\......\rx_bps_module.v
..........\......\rx_bps_module.v.bak
..........\......\RX_complete_module.v
..........\......\RX_complete_module.v.bak
..........\......\rx_control_module.v
..........\......\rx_control_module.v.bak
..........\......\rx_module.v
..........\......\rx_module.v.bak
..........\......\rx_top_control_module.v
..........\......\rx_top_control_module.v.bak
..........\......\RX_TX_FIFO.v
..........\......\RX_TX_FIFO.v.bak
..........\......\tx_bps_module.v
..........\......\tx_bps_module.v.bak
..........\......\TX_complete_module.v
..........\......\TX_complete_module.v.bak
..........\......\tx_control_module.v
..........\......\tx_control_module.v.bak
..........\......\tx_module.v
..........\......\tx_module.v.bak
..........\......\tx_top_control_module.v
..........\......\tx_top_control_module.v.bak
..........\......\greybox_tmp\cbx_args.txt
..........\.imulation\modelsim\RX_TX_FIFO.sft
..........\..........\........\RX_TX_FIFO.vho
..........\..........\........\RX_TX_FIFO_8_1200mv_0c_slow.vho
..........\..........\........\RX_TX_FIFO_8_1200mv_0c_vhd_slow.sdo
..........\..........\........\RX_TX_FIFO_8_1200mv_85c_slow.vho
..........\..........\........\RX_TX_FIFO_8_1200mv_85c_vhd_slow.sdo
..........\..........\........\RX_TX_FIFO_min_1200mv_0c_fast.vho
..........\..........\........\RX_TX_FIFO_min_1200mv_0c_vhd_fast.sdo
..........\..........\........\RX_TX_FIFO_modelsim.xrf
..........\..........\........\RX_TX_FIFO_vhd.sdo
..........\incremental_db\README
..........\..............\compiled_partitions\RX_TX_FIFO.db_info
..........\..............\...................\RX_TX_FIFO.root_partition.cmp.cdb
..........\..............\...................\RX_TX_FIFO.root_partition.cmp.dfp
..........\..............\...................\RX_TX_FIFO.root_partition.cmp.hdb
..........\..............\...................\RX_TX_FIFO.root_partition.cmp.kpt
..........\..............\...................\RX_TX_FIFO.root_partition.cmp.logdb
..........\..............\...................\RX_TX_FIFO.root_partition.cmp.rcfdb
..........\..............\...................\RX_TX_FIFO.root_partition.map.cdb
..........\..............\...................\RX_TX_FIFO.root_partition.map.dpi
..........\..............\...................\RX_TX_FIFO.root_partition.map.hbdb.cdb
..........\..............\...................\RX_TX_FIFO.root_partition.map.hbdb.hb_info
..........\..............\...................\RX_TX_FIFO.root_partition.map.hbdb.hdb
..........\..............\...................\RX_TX_FIFO.root_partition.map.hbdb.sig
..........\..............\...................\RX_TX_FIFO.root_partition.map.hdb
..........\..............\...................\RX_TX_FIFO.root_partition.map.kpt
..........\greybox_tmp\cbx_args.txt
..........\db\altsyncram_q0k1.tdf
..........\..\a_dpfifo_ca31.tdf
..........\..\a_fefifo_18e.tdf
..........\..\cntr_3ob.tdf
..........\..\cntr_fo7.tdf
..........\..\dpram_4711.tdf
..........\..\logic_util_heursitic.dat
..........\..\prev_cmp_RX_TX_FIFO.qmsg
..........\..\RX_TX_FIFO.db_info
..........\..\RX_TX_FIFO.sld_design_entry.sci
..........\..\scfifo_5431.tdf
..........\source\greybox_tmp
..........\.imulation\modelsim
..........\incremental_db\compiled_partitions
..........\source
..........\simulation
..........\incremental_db
..........\greybox_tmp
.....
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