VHDL-FPGA-Verilog List Page 881

VHDL-FPGA-Verilog list

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cic_filter Downloaded：0: 5 cic filter using vdhl written order to download the code will tb baked New, and then integrated simulation!
Date : 2025-07-28 Size : 2kb User :
verilog_ad7671 Downloaded：1: AD7671 FPGA-based control code is based on verilog language, it is practical, we hope to help
Date : 2025-07-28 Size : 1kb User : xuxiumin
ps2_vga Downloaded：0: Change program is written in VERILOG language to achieve VGA control PS2 mouse
Date : 2025-07-28 Size : 948kb User : 张东豪
8b_10b Downloaded：0: 8B10B encoding decoding
Date : 2025-07-28 Size : 71kb User : andi
uart_loop Downloaded：0: uart,Serial communication
Date : 2025-07-28 Size : 391kb User : zhouqianfei
COSTAS_LOOP Downloaded：0: Use ISE12.1 written Costas loop for carrier recovery, the direct use of the IP core of FIR and DDS module
Date : 2025-07-28 Size : 1kb User : nike
16QAM Downloaded：0: Verilog prepared using 16QAM modulation and demodulation code can be used quartus and ISE, because they do not contain FIR, only for simulation and not for actual communication
Date : 2025-07-28 Size : 5kb User : nike
collectdata_top Downloaded：0: SAA7113 data collect verilog code
Date : 2025-07-28 Size : 1kb User : 孙学斌
3.weigt-pattern-gen Downloaded：0: this IEEE based Vhdl Project accumlator based 3-weight pattern
Date : 2025-07-28 Size : 14.83mb User : parashu
18b20_code Downloaded：1: Temperature sensor design use DS18b20 thermometer, the temperature value is displayed on the digital control. Including source code, modelsim simulation and DS18B20 information related to PDF
Date : 2025-07-28 Size : 7.74mb User : 丛梦龙
SPCQF Downloaded：0: 8-way Responder design, the program uses language verilogHDL
Date : 2025-07-28 Size : 1.04mb User : 丛梦龙
AES_Enc_Dec_Final_Delivary Downloaded：0: this is IEEE vased nerwork project
Date : 2025-07-28 Size : 3.87mb User : parashu

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