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VHDL-FPGA-Verilog list
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This program description is bidirectional shift register using VHDL description of its functions, the reference for students
Date : 2025-07-28 Size : 114kb User : 魏银玲

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This program description is bidirectional buffer, using VHDL language to describe its function, the reference for students
Date : 2025-07-28 Size : 111kb User : 魏银玲

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This program is based on the RS flip-flop rs flip-flop functions described in VHDL language for students learning exchanges
Date : 2025-07-28 Size : 109kb User : 魏银玲

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This program is based on the jk flip-flop functions with VHDL description jk flip-flop for students learning exchanges
Date : 2025-07-28 Size : 108kb User : 魏银玲

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VHDL language describes the various gates, AND gates, OR gates, NAND, NAND, NOR, etc.
Date : 2025-07-28 Size : 770kb User : 魏银玲

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This procedure is used in light water vhdl language to describe the program, the function is left light water
Date : 2025-07-28 Size : 3kb User : 魏银玲

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This procedure is described using VHDL full adder program, designed to start from the top
Date : 2025-07-28 Size : 98kb User : 魏银玲

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FPGA-based design of the electronic code lock is a small digital system. It has many unique advantages:good privacy and security , it do not need the key but remember password to unlock, and so on while it compare to ord
Date : 2025-07-28 Size : 16kb User : zm

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DDR2 SDRAM High Performance Controller
Date : 2025-07-28 Size : 11.26mb User : zdwang

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There are times doc document verilog driver code ov7660 camera module, camera module can be achieved on the drive to achieve the corresponding functions of the camera
Date : 2025-07-28 Size : 16kb User : 刘佳毅

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VHDL code sample.this files is the VHDL code for using of DDR3 and DDR2 SDRAM.
Date : 2025-07-28 Size : 7kb User : homan

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After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication system
Date : 2025-07-28 Size : 13.74mb User : Nico_S
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