DDR2 SDRAM High Performance Controller

test_ddr2_ip
............\db
............\..\altpll_dyn_phase_le_0lo.tdf
............\..\altpll_dyn_phase_le_uko.tdf
............\..\altpll_dyn_phase_le_vko.tdf
............\..\altpll_mfl3.tdf
............\..\altsyncram_0jh1.tdf
............\..\altsyncram_7si1.tdf
............\..\altsyncram_f2e1.tdf
............\..\altsyncram_h2e1.tdf
............\..\altsyncram_jml1.tdf
............\..\altsyncram_lpl1.tdf
............\..\altsyncram_nvd1.tdf
............\..\a_dpfifo_dn31.tdf
............\..\a_dpfifo_po31.tdf
............\..\a_dpfifo_qo31.tdf
............\..\cmpr_909.tdf
............\..\cmpr_a09.tdf
............\..\cmpr_b09.tdf
............\..\cntr_3s7.tdf
............\..\cntr_4s7.tdf
............\..\cntr_5s7.tdf
............\..\cntr_mrb.tdf
............\..\cntr_nrb.tdf
............\..\cntr_orb.tdf
............\..\cntr_prb.tdf
............\..\ddio_bidir_h9h.tdf
............\..\ddio_bidir_lif.tdf
............\..\ddio_in_3kd.tdf
............\..\ddio_out_4od.tdf
............\..\ddio_out_hld.tdf
............\..\logic_util_heursitic.dat
............\..\scfifo_4c41.tdf
............\..\scfifo_gd41.tdf
............\..\scfifo_hd41.tdf
............\..\test_ddr_ip.amm.cdb
............\..\test_ddr_ip.cbx.xml
............\..\test_ddr_ip.cmp.bpm
............\..\test_ddr_ip.cmp.cdb
............\..\test_ddr_ip.cmp.hdb
............\..\test_ddr_ip.cmp.kpt
............\..\test_ddr_ip.cmp.logdb
............\..\test_ddr_ip.cmp.rdb
............\..\test_ddr_ip.cmp_merge.kpt
............\..\test_ddr_ip.db_info
............\..\test_ddr_ip.fit.qmsg
............\..\test_ddr_ip.hier_info
............\..\test_ddr_ip.hif
............\..\test_ddr_ip.idb.cdb
............\..\test_ddr_ip.lpc.html
............\..\test_ddr_ip.lpc.rdb
............\..\test_ddr_ip.lpc.txt
............\..\test_ddr_ip.map.bpm
............\..\test_ddr_ip.map.cdb
............\..\test_ddr_ip.map.hdb
............\..\test_ddr_ip.map.kpt
............\..\test_ddr_ip.map.logdb
............\..\test_ddr_ip.map.qmsg
............\..\test_ddr_ip.map_bb.cdb
............\..\test_ddr_ip.map_bb.hdb
............\..\test_ddr_ip.map_bb.logdb
............\..\test_ddr_ip.pre_map.cdb
............\..\test_ddr_ip.pre_map.hdb
............\..\test_ddr_ip.root_partition.map.reg_db.cdb
............\..\test_ddr_ip.rpp.qmsg
............\..\test_ddr_ip.rtlv.hdb
............\..\test_ddr_ip.rtlv_sg.cdb
............\..\test_ddr_ip.rtlv_sg_swap.cdb
............\..\test_ddr_ip.sgate.rvd
............\..\test_ddr_ip.sgate_sm.rvd
............\..\test_ddr_ip.sgdiff.cdb
............\..\test_ddr_ip.sgdiff.hdb
............\..\test_ddr_ip.sld_design_entry.sci
............\..\test_ddr_ip.sld_design_entry_dsc.sci
............\..\test_ddr_ip.smart_action.txt
............\..\test_ddr_ip.smp_dump.txt
............\..\test_ddr_ip.syn_hier_info
............\..\test_ddr_ip.tis_db_list.ddb
............\ddr2_ip
............\.......\altmemphy-library
............\.......\.................\auk_ddr_hp_controller.ocp
............\.......\alt_mem_ddrx_addr_cmd.v
............\.......\alt_mem_ddrx_addr_cmd_wrap.v
............\.......\alt_mem_ddrx_arbiter.v
............\.......\alt_mem_ddrx_buffer.v
............\.......\alt_mem_ddrx_buffer_manager.v
............\.......\alt_mem_ddrx_burst_gen.v
............\.......\alt_mem_ddrx_burst_tracking.v
............\.......\alt_mem_ddrx_cmd_gen.v
............\.......\alt_mem_ddrx_controller.v
............\.......\alt_mem_ddrx_controller_st_top.v
............\.......\alt_mem_ddrx_csr.v
............\.......\alt_mem_ddrx_dataid_manager.v
............\.......\alt_mem_ddrx_ddr2_odt_gen.v
............\.......\alt_mem_ddrx_ddr3_odt_gen.v
............\.......\alt_mem_ddrx_define.iv
............\.......\alt_mem_ddrx_ecc_decoder.v
............\.......\alt_mem_ddrx_ecc_decoder_32_syn.v
............\.......\alt_mem_ddrx_ecc_decoder_64_syn.v
............\.......\alt_mem_ddrx_ecc_encoder.v

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