JPEG Encoder IP Core,The core is written in Verilog and is designed to be portable to any target device. This core does not perform subsampling- the resulting JPEG image will have 4:4:4 subsampling

jpeg_encoder\cbd_q_h.v
............\cb_dct.v
............\cb_huff.v
............\cb_quantizer.v
............\crd_q_h.v
............\cr_dct.v
............\cr_huff.v
............\cr_quantizer.v
............\document\JPEG Encoder.doc
............\ff_checker.v
............\fifo_out.v
............\ja.jpg
............\ja.tif
............\ja_bits_out.v
............\jpeg_top.v
............\jpeg_top_TB.v
............\jpeg_top_TB_runtest.do
............\pre_fifo.v
............\Readme.doc
............\rgb2ycbcr.v
............\sync_fifo_32.v
............\sync_fifo_ff.v
............\yd_q_h.v
............\y_dct.v
............\y_huff.v
............\y_quantizer.v
............\document
jpeg_encoder

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