VHDL-FPGA-Verilog List Page 554

VHDL-FPGA-Verilog list

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ledall Downloaded：0: To achieve the dynamic LED dot matrix Chinese characters display design, by modifying the ROM module to change the display of Chinese characters
Date : 2025-06-22 Size : 536kb User : tom
Limi Downloaded：0: VHDL design with a 6-bit binary counter
Date : 2025-06-22 Size : 1kb User : 莫灵敏
ADC_TLC549 Downloaded：0: Based Verilog language TLC549 drive, drive digital control
Date : 2025-06-22 Size : 1.8mb User : 林安
DE2_115_TV Downloaded：0: 这个设计范例使用 DE2-115 上的 VGA 输出、音频编解码芯片以及 TV 解码芯片（ U6）播放来自 DVD 播放器输出的视频和音频信号。图 6-1 给出了设计的原理框图。系统主要由两个模块组成，它们是 I2C_AV_Config 以及 TV_to_VGA 模块。 TV_to_VGA 模块由 ITU-R 656 解码器， SDRAM 帧缓冲器， YUV422 转 YUV444， YcrCb 转 RGB 以及 VGA 控制器
Date : 2025-06-22 Size : 13.26mb User : gxhgxhgxh
DE2_115_Default Downloaded：0: DE2-115 出厂时写有默认的配置数据，用于演示开发板的一些基本特征。下面给出了默认配置的存放位置，和执行默认配置需要准备的工作。
Date : 2025-06-22 Size : 16.59mb User : gxhgxhgxh
LCD1602 Downloaded：0: FPGA 1602
Date : 2025-06-22 Size : 4.25mb User : 李海裴
clock Downloaded：0: FPGA clock
Date : 2025-06-22 Size : 1.98mb User : 李海裴
LCD12864 Downloaded：0: FPGA realization LCD12864 drive (embedded function generator required state machine), parallel data transmission, VHDL implementation.
Date : 2025-06-22 Size : 13.5mb User : WSong
DDS Downloaded：0: DDS on FPGA (VHDL), only FM, AM can be implemented in an external DA. (With triangular wave, sine wave, square wave rom call)
Date : 2025-06-22 Size : 534kb User : WSong
udp_ip_stack_latest.tar Downloaded：0: FPGA implementation using UDP/IP protocol to transfer
Date : 2025-06-22 Size : 18.84mb User : 朱诗迪
mips Downloaded：0: A single cycle CPU
Date : 2025-06-22 Size : 1.52mb User : 乔嘉林
DIVIDER Downloaded：0: Hello everyone, I am a graduate student at Fudan University. This resource is based on VHDL language of M bit by bit N divider. Where M/N, quotient M bits, the remainder is N bits. In Moim design verification and validat
Date : 2025-06-22 Size : 2kb User : ljt

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