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VHDL-FPGA-Verilog list
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Downloaded:0
NC divider design. It includes an even divide, and odd division.
Date
: 2025-06-22
Size
: 314kb
User
:
谢英才
AD9910
Downloaded:0
Based on Verilog AD9910 procedure, realization of QPSK modulation, just add a small amount of code can achieve 8PSK modulation
Date
: 2025-06-22
Size
: 5kb
User
:
kairukaichu
Downloaded:0
The use of open power system protection device in a program, only need to modify the address can be used with DSP together.
Date
: 2025-06-22
Size
: 152kb
User
:
wangfei
lishi
Downloaded:0
Flashing lights, digital tube counting 1000, for beginners to learn
Date
: 2025-06-22
Size
: 673kb
User
:
陈元
K7_1M
Downloaded:0
Ethernet drive-by Verilog language can achieve up to eight Ethernet, plus after PHY, can achieve a ping
Date
: 2025-06-22
Size
: 5.73mb
User
:
罗军
XC95288-optical-cable-host
Downloaded:0
This procedure is a host-based communications program light of CPLD95288 Xilinx chip development, AD7656AD capture capability.
Date
: 2025-06-22
Size
: 3kb
User
:
杜含宇
XC95288-optical-cable-slave
Downloaded:0
This procedure is based on Xilinx s CPLD95288 light communication chip development, AD7656AD acquisition the program.
Date
: 2025-06-22
Size
: 2kb
User
:
杜含宇
pll_zsy.v
Downloaded:0
All digital phase-locked loop based on VHDL write program this program can complete the relevant function
Date
: 2025-06-22
Size
: 374kb
User
:
赵政桐
fir_s
Downloaded:0
FIR filter source code and instantiated figure and waveform simulation diagram
Date
: 2025-06-22
Size
: 378kb
User
:
孙旭丽
cordic_new
Downloaded:0
cordic algorithm project.
Date
: 2025-06-22
Size
: 229kb
User
:
cuong
123455
Downloaded:0
32-bit accumulator, including 32-bit adder and register, procedures and simulation files included, can be run directly under the corresponding environment
Date
: 2025-06-22
Size
: 194kb
User
:
chaoshui
123456789
Downloaded:0
Waveform memory design using VHDL file can load some of the waveform data files contain simulation can be run directly Figure
Date
: 2025-06-22
Size
: 336kb
User
:
chaoshui
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