VHDL-FPGA-Verilog List Page 557

VHDL-FPGA-Verilog list

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lcd12864 Downloaded：0: lcd12864 VerilogHDL
Date : 2025-06-22 Size : 752kb User : 飞雪
key_led Downloaded：0: led control VerilogHDL
Date : 2025-06-22 Size : 375kb User : 飞雪
FIR-VHDL Downloaded：0: 15 order FIR filter design VHDL code, including the top-level module and each module VHDL design code
Date : 2025-06-22 Size : 2kb User : 张宇航
fpga_pid Downloaded：0: PID algorithm within the FPGA using feedback control the car speed and direction, four independent motors
Date : 2025-06-22 Size : 3kb User : xu
81245password Downloaded：0: Eight locks control circuit, when the DIP switch input eight binary number and password (preset bi nary number) are equal, the output signal to unlock the work of driving the actuator, with the red light, green light goe
Date : 2025-06-22 Size : 205kb User : 古德美尔
two_ADF4350_vhdl_code Downloaded：0: The realization of the program control: two ADF4350 VHDL program a plurality of gate signal coding.
Date : 2025-06-22 Size : 4kb User : 王乔
three_ADF4350_verilog_code Downloaded：0: The Verilog code to achieve control of the three ADF4350, with a test program.
Date : 2025-06-22 Size : 2kb User : 王乔
uart_tx Downloaded：0: Implementation serial port receive more frame data by software use Verilog, and has the function of the resist noise
Date : 2025-06-22 Size : 26kb User : 熊少
booth_mux4 Downloaded：0: Written on verilog of 4 booth algorithm
Date : 2025-06-22 Size : 2kb User : pilanjian
my_clock01 Downloaded：0: To achieve the electronic clock function with VHDL language
Date : 2025-06-22 Size : 8kb User : 赵海兵
chenxu Downloaded：0: Sequence Detection its design, testing 11100110.And through the seven-segment display decoder display.
Date : 2025-06-22 Size : 1kb User : 谢英才
DDSIP Downloaded：0: The program implements a sinusoidal function and cosine function data can be used as an input signal to other modules (direct call)
Date : 2025-06-22 Size : 1.14mb User : 于子轩

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