VHDL-FPGA-Verilog List Page 550

VHDL-FPGA-Verilog list

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PULSE_CDC Downloaded：0: Clock Domain Crossing (SLOW-to-FAST OR FAST-to-SLOW). This module transfers pulse IN clock domain to OUT clock
Date : 2025-06-22 Size : 1kb User : dimaz88
hostreg_make Downloaded：0: Verilog register creator based on text file input.
Date : 2025-06-22 Size : 4kb User : dimaz88
CIC_interpolator_wer1 Downloaded：0: CIC interpolation filter which DOESNT WORK
Date : 2025-06-22 Size : 1kb User : chujec
FPGAbasedprogramable-PROWER Downloaded：0: This design presents an FPGA-based programmable power supply solution. Input signal to FPGA, FPGA get ten and you, the count pulse signal, counting by the counter module, the internal counter signal all the way to an ext
Date : 2025-06-22 Size : 1.2mb User : 南宫崔浩
cpld-program Downloaded：0: CCD1208 drive timing, waveform meet the job requirements
Date : 2025-06-22 Size : 212kb User : 邢威
RISC_CPU Downloaded：0: RISC cpu design, verilog language, PIC14-bit instruction set
Date : 2025-06-22 Size : 342kb User : liuweijie
DDS Downloaded：0: FPGA, ISE12.2, DDS the code, VHDL language
Date : 2025-06-22 Size : 170kb User : liuweijie
emmc_cmd_interface_module Downloaded：2: emmc control chip CMD command line host interface module
Date : 2025-06-22 Size : 3kb User : Elkan
SRAM Downloaded：0: With SRAM memory compiler to generate 512* 8, tested, can read and write
Date : 2025-06-22 Size : 6kb User : 李中星
ahb Downloaded：0: Based AMBA2.0 the AHB bus, including the arbiter, decoder, Muxs2m, Muxm2s
Date : 2025-06-22 Size : 10kb User : 李中星
src_vtb Downloaded：0: With verilog realize Viterbi decoding circuit, Viterbi decoding can be achieved
Date : 2025-06-22 Size : 3kb User : 李中星
232Rec Downloaded：0: FPGA implemented in serial data received, the program is simple, using the Verilog language, clear thinking, a beginner s helper
Date : 2025-06-22 Size : 506kb User : ccm

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