VHDL-FPGA-Verilog List Page 546

VHDL-FPGA-Verilog list

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SOBLE_VGA Downloaded：0: This design is through the camera OV7670 capture images, and then through the FPGA edge detection algorithm, and finally through VGA display.
Date : 2025-06-21 Size : 1.49mb User : 马清源
fenpin Downloaded：0: Through the FPGA design of frequency divider module, simulation can be passed, for beginners to learn.
Date : 2025-06-21 Size : 294kb User : wanchun
FPGA_DSPbuilder Downloaded：0: DSPbuilder can be directly invoked in MATLAB to generate executable VHDL language.
Date : 2025-06-21 Size : 3.1mb User : wanchun
NIOS Downloaded：0: The use of II NIOS is introduced, that is, some functions can be realized through C language in FPGA.
Date : 2025-06-21 Size : 10.38mb User : wanchun
FPGA(lvbo) Downloaded：0: The filtering of the signal can be realized based on FPGA filtering
Date : 2025-06-21 Size : 137kb User : wanchun
music_keypad Downloaded：0: Using PPGA board to play musical note.
Date : 2025-06-21 Size : 478kb User : TashaYang
filters_FPGA2 Downloaded：0: this is vhdl code of median filter
Date : 2025-06-21 Size : 10kb User : aref
BarrelShifter3 Downloaded：1: this is vhdl code of BarrelShifter3
Date : 2025-06-21 Size : 319kb User : aref
dualpreiortyencoder Downloaded：0: this is vhdl code of dualpreiortyencoder
Date : 2025-06-21 Size : 56kb User : aref
sign-magnitude-adder Downloaded：0: this is vhdl code of sign-magnitude-adder
Date : 2025-06-21 Size : 103kb User : aref
FPGA-for-signal Downloaded：0: VHDL very good waveform generator Information
Date : 2025-06-21 Size : 12.05mb User : gsf
TEN Downloaded：0: TEN CONTER
Date : 2025-06-21 Size : 239kb User : afu

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