VHDL-FPGA-Verilog List Page 40

VHDL-FPGA-Verilog list

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Exp4TZ Downloaded：0: About the LED of PWM
Date : 2025-06-26 Size : 3.11mb User : xlxw
reactiontimer Downloaded：0: 1. Idle, which is the default state, is not responding to the test being executed. 2. This will inform users that a new reaction test is about to start. For example, users can notify the upcoming reaction test by countin
Date : 2025-06-26 Size : 1.6mb User : zhexigua
PC2FPGA_UART_Test Downloaded：0: UART design based on FPGA
Date : 2025-06-26 Size : 5.73mb User : 梦里千梦
vhdl Downloaded：1: The simulation of CD4527(BCD proportional multiplier)
Date : 2025-06-26 Size : 2kb User : 光速ZY
binary multiplier Downloaded：0: verilog code for binary multiplier
Date : 2025-06-26 Size : 3.58mb User : krisna
initial_lib Downloaded：0: The initial library file of Vivado contains 74LS series IP module and XUP series module.
Date : 2025-06-26 Size : 368kb User : 李航16
VmodCAM_Ref_HD Demo_13 Downloaded：0: This project has dependencies in the 'digilent' VHDL library. For your convenience a local copy of these dependencies are included in the remote_sources directory. The VmodCAM_Ref_HD demo project was built around an Atly
Date : 2025-06-26 Size : 13.13mb User : domnish
usb2.0调试助手 Downloaded：0: USB2.0 based C++ upper computer, measured available, for reference only.
Date : 2025-06-26 Size : 23.62mb User : feiyue324
28_ad9226_test Downloaded：0: This program has completed the acquisition of dual data. Through the ad module, the analog data is converted into 12 bit digital signals and is sent to the serial port assistant at the PC side through the serial port.
Date : 2025-06-26 Size : 3.21mb User : 张小er
ARS_SHA_1 Downloaded：0: The SHA-1 main control module realizes the control of the whole SHA-1 process.
Date : 2025-06-26 Size : 1kb User : anglo
FPGA实现AD8556采集程序设计 Downloaded：1: The design of FPGA data acquisition program based on ADS8556.
Date : 2025-06-26 Size : 15kb User : 小美玉
dpram Downloaded：0: generate DPRAM through verilog
Date : 2025-06-26 Size : 895kb User : isusan

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