VHDL-FPGA-Verilog List Page 35

VHDL-FPGA-Verilog list

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jiaotongdeng_fuza Downloaded：0: Based on the development of FPGA technology and the development platform of Quartus II, the realization of traffic lights controller at intersection is a solution. The Verilog HDL hardware description language is used to
Date : 2025-06-25 Size : 5.35mb User : 威威谈谈
eetop.cn_cordic_sqrt Downloaded：1: The CORDIC algorithm knows sine and cosine values and asks for inverse tangent, that is, angle.
Date : 2025-06-25 Size : 1kb User : 躲在岸上的鱼
CAN驱动器-MCP2515-接口程序-Verilog Downloaded：0: CAN driver MCP2515 driver, Verilog written, measured available
Date : 2025-06-25 Size : 9kb User : 天下布狼
dds Downloaded：0: Fang Bo, sine wave, triangle wave and sawtooth wave at any frequency are generated by key control
Date : 2025-06-25 Size : 3.95mb User : HUMBLE.
DBSTAR_RGMII Downloaded：0: Verilog implementation of RGMII and GMII interface transfer
Date : 2025-06-25 Size : 4.9mb User : zhzp
RS(204,188)译码器的设计 Downloaded：2: RS (204188) decoder explanation Original document: Rs_decoder.v (top level file), SyndromeCalc.v (Computational adjoint), BM_KES.v (BM solving key equations). Forney.v (Forney algorithm for error sample), CheinSearch.v (
Date : 2025-06-25 Size : 15kb User : HelloFrank0
ddc Downloaded：0: Detailed code and notes for down conversion sampling, local oscillator and filtering
Date : 2025-06-25 Size : 3kb User : 樨卡
Verilog Downloaded：0: aes digital audio interface from xilinx
Date : 2025-06-25 Size : 48kb User : SiamackBM
ldpc_decoder_802_3an Downloaded：0: The module of LDPC to implement the coding of the 802-3an protocol
Date : 2025-06-25 Size : 994kb User : fengyuanzyt
中级篇03：UART，波特率115200与PC通信 Downloaded：0: This program implements the serial communication function of the FPGA, and can transmit digital characters, etc., and the baud rate is 115200.
Date : 2025-06-25 Size : 10.07mb User : 小明d1
Altera+OpenCL Downloaded：0: Altera's OpenCL is mainly a client for signal processing applications, a tool for developing FPGA in the C language. The famous companies in the open computing language (OpenCL) alliance are FPGA giant Altera, two big ca
Date : 2025-06-25 Size : 457kb User : CrazyICer
float_mult32x32.v Downloaded：0: The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.
Date : 2025-06-25 Size : 1kb User : orangell

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