VHDL-FPGA-Verilog List Page 37

VHDL-FPGA-Verilog list

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10_100m_ethernet-fifo_convertor Downloaded：1: 10_100m_ethernet-fifo_convertor
Date : 2026-01-01 Size : 482kb User : 二叠好
DA输出控制LED亮度 Downloaded：0: Controlling the brightness of LED through digital to analog DA output is helpful to learn digital to analog conversion.
Date : 2026-01-01 Size : 820kb User : ~浮生若梦~
dsm3b Downloaded：1: 3bDSM for PLL which can achieve fractional divider ratio
Date : 2026-01-01 Size : 10kb User : alan114
vhdl交通灯 Downloaded：1: The realization of the intersection of two traffic lights function, complete experimental report, including source code
Date : 2026-01-01 Size : 1.11mb User : 无与伦比的
uart Downloaded：0: The implementation of the serial port and transceiver, can run stable
Date : 2026-01-01 Size : 7kb User : 小网忒小
counter Downloaded：0: An inverted timer based on FPGA
Date : 2026-01-01 Size : 3.02mb User : 奈歌
C51 Downloaded：0: Based on 51 single-chip environmental noise detector proteus simulation file containing a set of project files noise.dsn Keil main code main.c 6 relevant articles and graduation thesis design through simulation
Date : 2026-01-01 Size : 2kb User : 哈哈哈哈3
NIOS设计从入门到精通 Downloaded：1: nios tech.a very good book learning FPGA tech.
Date : 2026-01-01 Size : 2.81mb User : qianrnerui
OV7670 的SCCB (I2C)波形记录 Downloaded：0: OV7670 SCCB (I2C).pdf
Date : 2026-01-01 Size : 276kb User : 真萧瑟
《HELLO FPGA》- 软核演练篇 Downloaded：1: FPGA practice analysis requires detailed knowledge of these areas
Date : 2026-01-01 Size : 15.29mb User : bumblebee
XILINX平台DDR3设计教程 Downloaded：1: This is a zero to start Xilinx DDR3 control program written tutorial, the use of MIS IP kernel through the self compiled logic to achieve DDR3 reading and writing, strongly recommended.
Date : 2026-01-01 Size : 21.94mb User : 喵卡琳
电子时钟 Downloaded：1: Digital clock based on DE2-115 1. LCD display, digital tube display 2. whole point 3. alarm clock 4. setting time 5. set the alarm clock
Date : 2026-01-01 Size : 4.69mb User : AZ1111

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